Intel ULV 353 LE80536VC900512 Data Sheet
Product codes
LE80536VC900512
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet
17
counter and the performance monitor counters are not guaranteed to count in the Quick Start or
Sleep states. The local APIC timer and performance monitor counter interrupts should be disabled
before entering the Deep Sleep state or the resulting behavior will be unpredictable.
Sleep states. The local APIC timer and performance monitor counter interrupts should be disabled
before entering the Deep Sleep state or the resulting behavior will be unpredictable.
2.3 GTL+
Signals
The mobile Intel Celeron processor system bus signals use a variation of the low-voltage swing
GTL signaling technology. The mobile Intel Celeron processor system bus specification is similar
to the Pentium II processor system bus specification, which is a version of GTL with enhanced
noise margins and less ringing.
GTL signaling technology. The mobile Intel Celeron processor system bus specification is similar
to the Pentium II processor system bus specification, which is a version of GTL with enhanced
noise margins and less ringing.
The GTL+ system bus depends on incident wave switching and uses flight time for timing
calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of
the system bus including trace lengths is highly recommended. Contact your field sales
representative to receive the IBIS models for the mobile Intel Celeron processor.
calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of
the system bus including trace lengths is highly recommended. Contact your field sales
representative to receive the IBIS models for the mobile Intel Celeron processor.
The GTL+ system bus of the Celeron processor was designed to support high-speed data transfers
with multiple loads on a long bus that behaves like a transmission line. However, in mobile
systems the system bus only has two loads (the processor and the chipset) and the bus traces are
short. It is possible to change the layout and termination of the system bus to take advantage of the
mobile environment using the same GTL+ I/O buffers. In mobile systems the GTL+ system bus is
terminated at one end only. This termination is provided on the processor core (except for the
RESET# signal). Refer to the Mobile Pentium® III Processor GTL+ System Bus Layout Guideline
for details on laying out the GTL+ system bus.
with multiple loads on a long bus that behaves like a transmission line. However, in mobile
systems the system bus only has two loads (the processor and the chipset) and the bus traces are
short. It is possible to change the layout and termination of the system bus to take advantage of the
mobile environment using the same GTL+ I/O buffers. In mobile systems the GTL+ system bus is
terminated at one end only. This termination is provided on the processor core (except for the
RESET# signal). Refer to the Mobile Pentium® III Processor GTL+ System Bus Layout Guideline
for details on laying out the GTL+ system bus.
2.4
Mobile Intel Celeron processor CPUID
When the CPUID version information is loaded with EAX=01H, the EAX and EBX registers
contain the values shown in Table 4. After a power-on RESET, the EDX register contains the
processor version information (type, family, model, stepping). See Intel Processor Identification
and the CPUID Instruction Application Note AP-485 for further information.
contain the values shown in Table 4. After a power-on RESET, the EDX register contains the
processor version information (type, family, model, stepping). See Intel Processor Identification
and the CPUID Instruction Application Note AP-485 for further information.
Table 4. Mobile Intel Celeron Processor CPUID
EAX[31:0] EBX[7:0]
Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0] Brand ID
X 0
6
8
X
01
After the L2 cache is initialized, the CPUID cache/TLB descriptors will be the values shown in
Table 5.
Table 5.
Table 5. Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors
Cache and TLB Descriptors
01H, 02H, 03H, 04H, 08H, 0CH, 41H