Intel ULV 373 LE80536VC001512 Data Sheet
Product codes
LE80536VC001512
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
Datasheet
283654-003
28
3.6 AC
Specifications
3.6.1
System Bus, Clock, APIC, TAP, CMOS, and Open-drain AC
Specifications
Specifications
Table 13 through Table 21 provide AC specifications associated with the mobile Intel Celeron
processor. The AC specifications are divided into the following categories: Table 13 contains the
system bus clock specifications; Table 14 contains the processor core frequencies; Table 15
contains the GTL+ specifications; Table 16 contains the CMOS and Open-drain signal groups
specifications; Table 17 contains timings for the reset conditions; Table 18 contains the APIC
specifications; Table 19 contains the TAP specifications; and Table 20 and Table 21 contain the
power management timing specifications.
processor. The AC specifications are divided into the following categories: Table 13 contains the
system bus clock specifications; Table 14 contains the processor core frequencies; Table 15
contains the GTL+ specifications; Table 16 contains the CMOS and Open-drain signal groups
specifications; Table 17 contains timings for the reset conditions; Table 18 contains the APIC
specifications; Table 19 contains the TAP specifications; and Table 20 and Table 21 contain the
power management timing specifications.
All system bus AC specifications for the GTL+ signal group are relative to the rising edge of the
BCLK input at 1.25V. All GTL+ timings are referenced to V
BCLK input at 1.25V. All GTL+ timings are referenced to V
REF
for both “0” and “1” logic levels
unless otherwise specified. All APIC, TAP, CMOS, and Open-drain signals except PWRGOOD
are referenced to 0.75V.
are referenced to 0.75V.
Table 13. System Bus Clock AC Specifications
1
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 1.10V ±80 mV or 1.15V ±80 mV or 1.35V
±100 mV or 1.60V ±115; V
CCT
= 1.50V ±115 mV
Symbol Parameter
Min Typ Max Unit Figure
Notes
System
Bus
Frequency
100
MHz
T1
BCLK Period
10
ns
Note 2
T2
BCLK Period Stability
±250
ps
Notes 3, 4
T3
BCLK High Time
2.70
ns
at >2.0V
T4
BCLK Low Time
2.45
ns
at <0.5V
T5
BCLK Rise Time
0.175
0.875
ns
(0.9V – 1.6V)
T6
BCLK Fall Time
0.175
0.875
ns
(1.6V – 0.9V)
NOTES:
1.
All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25V. All CMOS
signals are referenced at 0.75V.
signals are referenced at 0.75V.
2.
The BCLK period allows a +0.5 ns tolerance for clock driver variation.
3.
Not 100% tested. Specified by design/characterization.
4.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a
component of BCLK skew between devices.
component of BCLK skew between devices.