Intel ULV 373 LE80536VC001512 Data Sheet
Product codes
LE80536VC001512
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet
45
Table 26. Non-GTL+ Signal Group Overshoot/Undershoot Tolerance at the Processor Core
1, 4, 5
Overshoot Amplitude
2
Undershoot
Amplitude
3
Allowed Pulse Duration
2.1V -0.45V
0.45
ns
2.0V -0.35V
1.5
ns
1.9V -0.25V
5.0
ns
1.8V -0.15V
17
ns
NOTES:
1.
Under no circumstances should the non-GTL+ signal voltage ever exceed 2.1V maximum with respect to
ground or -2.1V minimum with respect to V
ground or -2.1V minimum with respect to V
CCT
(i.e., V
CCT
- 2.1V) under operating conditions.
2.
Ring-backs below V
CCT
cannot be subtracted from overshoots. Lesser undershoot does not allocate longer
or larger overshoot.
3.
Ring-backs above ground cannot be subtracted from undershoots. Lesser overshoot does not allocate
longer or larger undershoot.
longer or larger undershoot.
4.
System designers are encouraged to follow Intel provided non-GTL+ layout guidelines.
5.
All values are specified by design characterization, and are not tested.
4.3.1
PWRGOOD Signal Quality Specifications
The processor requires PWRGOOD to be a clean indication that clocks and the power supplies
(V
(V
CC
, V
CCT
, etc.) are stable and within their specifications. Clean implies that the signal will
remain below V
IL25
and without errors from the time that the power supplies are turned on, until
they come within specification. The signal will then transition monotonically to a high (2.5V)
state. PWRGOOD may not ringback below 2.0V after rising above V
state. PWRGOOD may not ringback below 2.0V after rising above V
IH25
.