Intel ULV 373 LE80536VC001512 Data Sheet

283654-003 Datasheet 

 

 

61 

The mobile Intel Celeron processor has some configuration options that are determined by 
hardware and some that are determined by software. The processor samples its hardware 
configuration at reset on the active-to-inactive transition of RESET#. Most of the configuration 
options for the mobile Intel Celeron processor are identical to those of the Pentium II processor. 
The Pentium

 II Processor Developer’s Manual describes these configuration options. New 

configuration options for the mobile Intel Celeron processor are described in the remainder of this 
section. 

The processor normally enters the Stop Grant state when the STPCLK# signal is asserted but it 
will enter the Quick Start state instead if A15# is sampled active on the RESET# signal’s active-
to-inactive transition. The Quick Start state supports snoops from the bus priority device like the 
Stop Grant state but it does not support symmetric master snoops nor is the latching of interrupts 
supported. A “1” in bit position 5 of the Power-on Configuration register indicates that the Quick 
Start state has been enabled. 

The current generation mobile Intel Celeron processor will only function with a system bus 
frequency of 100 MHz. Bit positions 18 to 19 of the Power-on Configuration register indicates at 
which speed a processor will run. A “00” in bits [19:18] indicates a 66-MHz bus frequency, a “10” 
indicates a 100-MHz bus frequency, and a “01” indicates a 133-MHz bus frequency.  

If the PICD0 signal is sampled low on the active-to-inactive transition of the RESET# signal then 
the PICCLK signal can be tied to V

SS

. Otherwise the PICD[1:0] signals must be pulled up to V

CCT

 

and PICCLK must be supplied. Driving PICD0 low at reset also has the effect of clearing the 
APIC Global Enable bit in the APIC Base MSR. This bit is normally set when the processor is 
reset, but when it is cleared the APIC is completely disabled until the next reset. 

The mobile Intel Celeron processor uses a clock design in which the bus clock is multiplied by a 
ratio to produce the processor’s internal (or “core”) clock. Unlike some of the mobile Pentium II 
processor, the ratio used is programmed into the processor during manufacturing. The bus ratio 
programmed into the processor is visible in bit positions 22 to 25, and 27 of the Power-on