Intel III Xeon 933 MHz 80526KB933256 Data Sheet
Product codes
80526KB933256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
APPENDIX
100
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power Stop Grant state. The
processor issues a Stop Grant Acknowledge transaction, and stops providing internal clock signals to all processor core
units except the bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in
Stop Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.
processor issues a Stop Grant Acknowledge transaction, and stops providing internal clock signals to all processor core
units except the bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in
Stop Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.
10.1.54 TCK (I)
The TCK (Test Clock) signal provides the clock input for the Pentium® III Xeon™ processor at 600 MHz+ Test Bus (also
known as the Test Access Port).
known as the Test Access Port).
10.1.55 TDI (I)
The TDI (Test Data In) signal transfers serial test data into the Pentium III Xeon processor at 600 MHz+. TDI provides the
serial input needed for TAP support.
serial input needed for TAP support.
10.1.56 TDO (O)
The TDO (Test Data Out) signal transfers serial test data out of the Pentium III Xeon processor at 600 MHz+. TDO
provides the serial output needed for TAP support.
provides the serial output needed for TAP support.
10.1.57 TEST_2.5_[A23, A62, B27] (I)
The TEST_2.5_A62 signal must be connected to a 2.5V power source through a 1-10K ohm
resistor for proper processor
operation.
10.1.58 THERMTRIP# (O)
This pin indicates a thermal overload condition (thermal trip). The processor protects itself from catastrophic overheating
by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there
are no false trips. The processor will immediately stop all execution when the junction temperature exceeds approximately
135°C. This is signaled to the system by the THERMTRIP# pin. Once activated, the signal remains latched, and the
processor stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself. Once the die
temperature drops below the trip level, a RESET# pulse will reinitialize the processor and execution will continue at the
reset vector. If the temperature has not dropped below the trip level, the processor will continue to drive THERMTRIP#
and remain stopped regardless of the state of RESET#.
by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there
are no false trips. The processor will immediately stop all execution when the junction temperature exceeds approximately
135°C. This is signaled to the system by the THERMTRIP# pin. Once activated, the signal remains latched, and the
processor stopped, until RESET# goes active. There is no hysteresis built into the thermal sensor itself. Once the die
temperature drops below the trip level, a RESET# pulse will reinitialize the processor and execution will continue at the
reset vector. If the temperature has not dropped below the trip level, the processor will continue to drive THERMTRIP#
and remain stopped regardless of the state of RESET#.
The system designer should not act upon THERMTRIP# until after the RESET# input is de-asserted. Until this time, the
THERMTRIP# output is indeterminate.
THERMTRIP# output is indeterminate.
10.1.59 TMS (I)
The TMS (Test Mode Select) signal is a TAP support signal used by debug tools.
10.1.60 TRDY# (I)
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit
writeback data transfer. TRDY# must connect the appropriate pins of all Pentium III Xeon processor at 600 MHz+ system
bus agents.
writeback data transfer. TRDY# must connect the appropriate pins of all Pentium III Xeon processor at 600 MHz+ system
bus agents.
10.1.61 TRST# (I)
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. Pentium III Xeon processor at 600 MHz+ self-
reset during power on; therefore, it is not necessary to drive this signal during power on reset.
reset during power on; therefore, it is not necessary to drive this signal during power on reset.
10.1.62 VID_L2[4:0], VID_CORE[4:0] (O)
The VID (Voltage ID) pins can be used to support automatic selection of power supply voltages. These pins are not
signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts
defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification variations
on Pentium® III Xeon™ processor at 600 MHz+ and Pentium® III Xeon™ processors. See Table 2 for definitions of these
signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts
defines the voltage required by the processor. The VID pins are needed to cleanly support voltage specification variations
on Pentium® III Xeon™ processor at 600 MHz+ and Pentium® III Xeon™ processors. See Table 2 for definitions of these