Intel III Xeon 933 MHz 80526KB933256 Data Sheet
Product codes
80526KB933256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
ELECTRICAL SPECIFICATIONS
24
Table 13. AGTL+ Signal Group, System Bus AC Specifications at the processors Core
1
R
L
= 50 ohms Terminated to 1.5V
T#
Parameter
Min
Max
Unit
Figure
Notes
T7:
AGTL+ Output Valid Delay
-0.05
2.65
nS
Figure 5
2
T8:
AGTL+ Input Setup Time
1.2
nS
Figure 6
3, 4, 6
T9:
AGTL+ Input Hold Time
0.80
nS
Figure 6
5
T10:
RESET# Pulse Width
1.00
mS
Figure 8
5
NOTES:
1.
These specifications are tested during manufacturing.
2.
Valid delay timings for these signals at the processor core assume a 50 ohms termination to 1.5V.
3.
A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
4.
RESET# can be asserted (active) asynchronously, but must be deasserted synchronously to the bus clock.
5.
After the bus ratio on A20M#, IGNNE# and LINT[1:0] are stable,
VCC_CORE
, and BCLK are within specification, and PWRGD is
asserted. See Figure 8, 40 & 41.
6.
Specification is for a minimum 0.40V swing from V
REF
- 200 mV to V
REF
+ 200 mV. This assumes an edge rate of .3V/ns
Table 14. CMOS, TAP, Clock and APIC Signal Groups, AC Specifications at the processor Core
1, 2
T#
Parameter
Min
Max
Unit
Figure
Notes
T14:
CMOS Input Pulse Width,
except PWRGD and
LINT[1:0]
except PWRGD and
LINT[1:0]
2
BCLKs
Figure 5
Active and Inactive
states
T14B: LINT[1:0] Input Pulse Width
6
BCLKs
Figure 5
3
T15:
PWRGD Inactive Pulse
Width
Width
10
BCLKs
Figure 5
Figure 9
4
NOTES:
1.
These specifications are tested during manufacturing.
2.
Valid delay timings for these signals are specified into 100 ohms to 2.5V.
3.
When driven inactive or after
VCC_CORE
, and BCLK become stable. PWRGD must remain below V
IL_MAX
from Table 8 until all the
voltage planes meet the voltage tolerance specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 11 for at
least 10 clock cycles. PWRGD must rise glitch-free and monotonically to 2.5V.
least 10 clock cycles. PWRGD must rise glitch-free and monotonically to 2.5V.
4.
If the BCLK signal meets its AC specification within 150ns of turning on then the PWRGD Inactive Pulse Width specification is waived
and BCLK may start after PWRGD is asserted. PWRGD must still remain below V
and BCLK may start after PWRGD is asserted. PWRGD must still remain below V
IL_MAX
until all the voltage planes meet the voltage
tolerance specifications.