Intel III Xeon 933 MHz 80526KB933256 Data Sheet

91

The BR[3:1]# (Bus Request) pins drive the BREQ[3:0]# signals on the system. The BR[3:0]# pins are interconnected in a
rotating manner to other processors’ BR[3:0]# pins.

Table  49 gives the interconnect between the processor and bus signals for a 2-way system.

BREQ0#

BR0#

BR3#

BREQ1#

BR1#

BR0#

BREQ2#

N/C

N/C

BREQ3#

N/C

N/C

During power-up configuration, the central agent must assert its BR0# signal. All symmetric agents sample their BR[3:0]#
pins on active-to-inactive transition of RESET#. The pin on which the agent samples an active level determines its agent
ID. All agents then configure their BREQ[3:0]# signals to match the appropriate bus signal protocol, as shown in Table 50.

L

H

H

H

0

H

H

H

L

1

H

H

L

H

2

H

L

H

H

3

The Pentium III Xeon processor at 600 MHz+ uses a reduced set of signals. The Pentium III Xeon processor at 600 MHz+
supports 2-Way configurations only. On a Pentium III Xeon processor at 600 MHz+ cartridge only BR0#, BR1# and BR3#
(Bus Request) pins drive the BREQ[3:0]# signals on the system. An assertion to BR2# has no effect since it is not seen at
the processor.

The BR[3]# and BR[1:0]# pins are interconnected in a rotating manner to other processor’s BR[3]# and BR[1:0]# pins. The
following table gives the rotating interconnect between the processor and bus signals for 2-way systems

.