Intel ULV 423 LE80538VE0041M Data Sheet
Product codes
LE80538VE0041M
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
283654-003 Datasheet
29
Table 14. Valid Mobile Intel Celeron Processor Frequencies
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 1.10V ±80 mV or 1.15V ±80 mV or 1.35V
±100 mV or 1.60V ±115; V
CCT
= 1.50V ±115 mV
BCLK Frequency
(MHz)
Frequency Multiplier
Core Frequency
(MHz)
Power-on Configuration
bits [27, 25:22]
100 4.0
400A
0,
0010
100 4.5 450
0,
0110
100 5.0 500
0,
0000
100 5.5 550
0,
0100
100 6.0 600
0,
1011
100 6.5 650
0,
1111
100 7.0 700
0,
1001
100 7.5 750
0,
1101
100 8 800
0,
1010
100 8.5 850
1,
0110
100 9 900
1,
0000
Table 15. GTL+ Signal Groups AC Specifications
1
R
TT
=
56Ω
internally
terminated to
V
CCT
;
V
REF
=
2
/
3
V
CCT
; load = 0 pF;
T
J
= 0°C to 100°C; T
J
= 5°C to 100°C for Vcc = 1.15V; V
CC
= 1.10V ±80 mV or 1.15V ±80 mV or 1.35V ±100
mV or 1.60V ±115; V
CCT
= 1.50V ±115 mV
Symbol Parameter
Min
Max
Unit
Figure Notes
T7
GTL+ Output Valid Delay
0.2
0.2
0.2
2.7
3.4
3.4
ns
Note 6
Note 7
Note 7
T8
GTL+ Input Setup Time
1.2
ns
Notes 2, 3
T9
GTL+ Input Hold Time
0.80
1.2
1.2
ns
Note 4, 6
Note 7
Note 7
T10
RESET# Pulse Width
1.0
ms
Note 5
NOTES:
1.
All AC timings for GTL+ signals are referenced to the BCLK rising edge at 1.25V. All GTL+ signals are
referenced at V
referenced at V
REF
.
2.
RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
3.
Specification is for a minimum 0.40V swing.
4.
Specification is for a maximum 1.0V swing.
5.
After V
CC
, V
CCT
, and BCLK become stable and PWRGOOD is asserted.
6.
Applies to all core Vcc other than 1.10V
7.
Applies only to core Vcc = 1.10V