Intel III Xeon 550 MHz 80525KY550512 User Manual
Product codes
80525KY550512
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
27
BCLK has met the BCLK AC specifications in
for at least 10 clock cycles. PWRGOOD must rise
glitch-free and monotonica lly to 2.5V.
8. If the BCLK signal meets its AC specification withi n 150ns of turning on then the PWRGOOD Inactive Pulse
Width specification is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still
remain below V
remain below V
IL_MAX
until all the voltage planes meet the voltage tolerance specifications.
†
For a Reset, the clock ratio defined by these signals must be a safe value (their final or lower multiplier) within
this delay unless PWRGOOD is being driven inactive.
this delay unless PWRGOOD is being driven inactive.
NOTE:
1. These specifications are tested during manufacturing.
2. With FRC enabled PICCLK must be 1/4 of BCLK and synchronized with respect to BCLK.
3. Referenced to PICCLK rising edge.
4. For open drain signals, valid delay is synonymous with float delay.
5. Valid delay timings for these signals are specif i ed to 2.5V.
2. With FRC enabled PICCLK must be 1/4 of BCLK and synchronized with respect to BCLK.
3. Referenced to PICCLK rising edge.
4. For open drain signals, valid delay is synonymous with float delay.
5. Valid delay timings for these signals are specif i ed to 2.5V.
Table 14. System Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T16:
Reset Configuration Signals (A[14:05]#,
BR0#, FLUSH#, INIT#) Setup Time
BR0#, FLUSH#, INIT#) Setup Time
4
BCLKs
Before deassertion of
RESET
RESET
T17: Reset
Configuration
Signals
(A[14:05]#,
BR0#, FLUSH#, INIT#) Hold Time
2
20
BCLKs
After clock that
deasserts RESET#
deasserts RESET#
T18: Reset
Configuration
Signals
(A20M#,
IGNNE#, LINT[1:0]) Setup Time
1
ms
Before deassertion of
RESET#
RESET#
T19: Reset
Configuration
Signals
(A20M#,
IGNNE#, LINT[1:0]) Delay Time
5
BCLKs
After assertion of
RESET#
RESET#
†
T20: Reset
Configuration
Signals
(A20M#,
IGNNE#, LINT[1:0]#) Hold Time
2
20
BCLKs
After clock that
deasserts RESET#
deasserts RESET#
Table 15. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core
1
T# Parameter
Min
Max
Unit
Figure
Notes
T21: PICCLK
Frequency
2.0
33.3
MHz
2
T21B: FRC Mode BCLK to PICCLK Offset
1.0
4.0
ns
2
T22: PICCLK
Period
30.0
500.0
ns
T23: PICCLK
High
Time
12.0
ns
T24: PICCLK
Low
Time
12.0
ns
T25: PICCLK
Rise
Tim
0.25
3.0
ns
T26: PICCLK
Fall
Time
0.25
3.0
ns
T27: PICD[1:0] Setup Time
8.0
ns
3
T28: PICD[1:0]
Hold
Time
2.5
ns
3
T29: PICD[1:0] Valid Delay
1.5
10.0
ns
3, 4, 5