Intel III Xeon 550 MHz 80525KY550512 User Manual

Intel

Product codes

80525KY550512

Pentium

®

III Xeon™ Processor at 500 and 550 MHz

6

Datasheet

9.1.47 SLP# (I) ..................................................................................................96
9.1.48 SMBALERT# (O)....................................................................................96
9.1.49 SMBCLK (I) ............................................................................................96
9.1.50 SMBDAT (I/O) ........................................................................................96
9.1.51 SMI# (I) ..................................................................................................96
9.1.52 STPCLK# (I)...........................................................................................97
9.1.53 TCK (I)....................................................................................................97
9.1.54 TDI (I) .....................................................................................................97
9.1.55 TDO (O) .................................................................................................97
9.1.56 TEST_25_A62 (I) ...................................................................................97
9.1.57 TEST_VCC_CORE_XXX (I)...................................................................97
9.1.58 THERMTRIP# (O) ..................................................................................97
9.1.59 TMS (I) ...................................................................................................98
9.1.60 TRDY# (I) ...............................................................................................98
9.1.61 TRST# (I) ...............................................................................................98
9.1.62 VID_L2[4:0], VID_CORE[4:0](O)............................................................98
9.1.63 WP (I) .....................................................................................................98

Signal Summaries ...............................................................................................98

Figures

Timing Diagram of Clock Ratio Signals............................................................... 15

Logical Schematic for Clock Ratio Pin Sharing................................................... 15

I-V Curve for nMOS Device.................................................................................23

BCLK, PICCLK, TCK Generic Clock Waveform.................................................. 29

SMBCLK Clock Waveform ..................................................................................29

Valid Delay Timings ............................................................................................29

Setup and Hold Timings......................................................................................30

FRC Mode BCLK to PICCLK Timing...................................................................30

System Bus Reset and Configuration Timings.................................................... 31

Power-On Reset and Configuration Timings....................................................... 31

Test Timings (Boundary Scan)............................................................................32

Test Reset Timings .............................................................................................32

BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins...... 33

Low to High AGTL+ Receiver Ringback Tolerance............................................. 34

Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback ..................... 35

Stop Clock State Machine...................................................................................38

Logical Schematic of SMBus Circuitry ................................................................ 40

Thermal Plate View .............................................................................................50

Plate Flatness Reference....................................................................................51

Interface Agent Dispensing Areas and Thermal Plate Temperature
Measurement Points ...........................................................................................53

Technique for Measuring T

PLATE

with 0° Angle Attachment ............................... 54

Technique for Measuring T

PLATE

with 90° Angle Attachment ............................. 54

Guideline Locations for Cover Temperature (T

) Thermocouple

Placement ...........................................................................................................55

Isometric View of Pentium

®

III Xeon™ Processor S.E.C. Cartridge ................... 56

S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure 27) ........ 57

S.E.C. Cartridge Retention Enabling Details (Notes follow Figure 27) ............... 58

S.E.C. Cartridge Retention Enabling Details....................................................... 59

Side View of Connector Mating Details............................................................... 60