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Intel III Xeon 550 MHz 80525KY550512 User Manual

Product codes
80525KY550512
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Pentium
® 
III Xeon™ Processor at 500 and 550 MHz
62
Datasheet
6.3
Pentium
®
 III Xeon™ Processor Substrate Edge Finger 
Signal Listing
 is the Pentium 
III
 Xeon processor substrate edge finger listing in order by pin number
 is the Pentium 
III
 Xeon processor substrate edge connector listing in order by pin name.
Table 40.  Signal Listing in Order by Pin Number  (Sheet 1 of 4)
Pin
No.
Pin Name
Signal Buffer Type
Pin
No.
Pin Name
Signal Buffer Type
A1
EMI
Connect to V
SS
 
B1
PWR_EN[1]
Short to PWR_EN[0]
A2
VCC_TAP
TAP Supply
B2
VCC_CORE
CPU Core V
CC
A3
EMI
Connect to V
SS
 
B3
RESERVED_B3
DO NOT CONNECT
A4
VSS
Ground
B4
TEST_VSS_B4
Pull down to V
SS
A5
VTT
AGTL+ V
TT
 Supply
B5
VCC_CORE
CPU Core V
CC
A6
VTT
AGTL+ V
TT
 Supply
B6
VTT
AGTL+ V
TT
 Supply
A7
SELFSB1
CMOS I/O
B7
VTT
AGTL+ V
TT
 Supply
A8
VSS
Ground
B8
VCC_CORE
CPU Core V
CC
A9
SELFSB0
CMOS I/O
B9
RESERVED_B9
DO NOT CONNECT
A10
VSS
Ground
B10
FLUSH#
CMOS Input
A11
TEST_VSS_A11
Pull down to V
SS
B11
VCC_CORE
CPU Core V
CC
A12
IERR#
CMOS Output
B12
SMI#
CMOS Input
A13
VSS
Ground
B13
INIT#
CMOS Input
A14
A20M#
CMOS Input
B14
VCC_CORE
CPU Core V
CC
A15
FERR#
CMOS Output
B15
STPCLK#
CMOS Input
A16
VSS
Ground
B16
TCK
TAP Clock
A17
IGNNE#
CMOS Input
B17
VCC_CORE
CPU Core V
CC
A18
TDI
TAP Input
B18
SLP#
CMOS Input
A19
VSS
Ground
B19
TMS
TAP Input
A20
TDO
TAP Output
B20
VCC_CORE
CPU Core V
CC
A21
PWRGOOD
CMOS Input
B21
TRST#
TAP Input
A22
VSS
Ground
B22
RESERVED_B22
DO NOT CONNECT
A23
TEST_VCC_CORE_A23 Pull up to VCC_CORE
B23
VCC_CORE
CPU Core V
CC
A24
THERMTRIP#
CMOS Output
B24
RESERVED_B24
DO NOT CONNECT
A25
VSS
Ground
B25
RESERVED_B25
DO NOT CONNECT
A26
RESERVED_A26
DO NOT CONNECT
B26
VCC_CORE
CPU Core V
CC
A27
LINT[0]
CMOS Input
B27
TEST_VCC_CORE_B27
Pull up to VCC_CORE
A28
VSS
Ground
B28
LINT[1]
CMOS Input
A29
PICD[0]
CMOS I/O
B29
VCC_CORE
CPU Core V
CC
A30
PREQ#
CMOS Input
B30
PICCLK
APIC Clock Input
A31
VSS
Ground
B31
PICD[1]
CMOS I/O
A32
BP#[3]
AGTL+ I/O
B32
VCC_CORE
CPU Core V
CC
A33
BPM#[0]
AGTL+ I/O
B33
BP#[2]
AGTL+ I/O
A34
VSS
Ground
B34
RESERVED_B34
DO NOT CONNECT
A35
BINIT#
AGTL+ I/O
B35
VCC_CORE
CPU Core V
CC
A36
DEP#[0]
AGTL+ I/O
B36
PRDY#
AGTL+ Output
A37
VSS
Ground
B37
BPM#[1]
AGTL+ I/O