Intel ULV 383 LE80536VC0011M Data Sheet
Product codes
LE80536VC0011M
Mobile Intel
®
Celeron
®
Processor (0.18µ) in BGA2 and Micro-PGA2 Packages
Datasheet
283654-003
10
1.1 Overview
•
Performance improved over existing mobile processors
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Supports the Intel Architecture with Dynamic Execution
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Supports the Intel Architecture MMX™ technology
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Supports Streaming SIMD Extensions for enhanced video, sound, and 3D performance
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Integrated Intel Floating Point Unit compatible with the IEEE 754 standard
•
On-die primary (L1) instruction and data caches
−
4-way set associative, 32-byte line size, 1 line per sector
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16-Kbyte instruction cache and 16-Kbyte write-back data cache
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Cacheable range controlled by processor programmable registers
•
On-die second level (L2) cache
−
4-way set associative, 32-byte line size, 1 line per sector
−
Operates at full core speed
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128-Kbyte, ECC protected cache data array
•
GTL+ system bus interface
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64-bit data bus, 100-MHz operation
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Uniprocessor, two loads only (processor and I/O bridge/memory controller)
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Integrated termination
•
Mobile Pentium II processor clock control
−
Quick Start for low power, low exit latency clock “throttling”
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Deep Sleep mode for even lower power dissipation
•
Thermal diode for measuring processor temperature
1.2 Terminology
In this document a “#” symbol following a signal name indicates that the signal is active low. This
means that when the signal is asserted (based on the name of the signal) it is in an electrical low
state. Otherwise, signals are driven in an electrical high state when they are asserted. In state
machine diagrams, a signal name in a condition indicates the condition of that signal being
asserted. If the signal name is preceded by a “!” symbol, then it indicates the condition of that
signal not being asserted. For example, the condition “!STPCLK# and HS” is equivalent to “the
active low signal STPCLK# is unasserted (i.e., it is at 1.5V) and the HS condition is true.” The
symbols “L” and “H” refer respectively to electrical low and electrical high signal levels. The
symbols “0” and “1” refer respectively to logical low and logical high signal levels. For example,
BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” = “LHLH” also
refers to a hexadecimal “A.” The symbol “X” refers to a “Don’t Care” condition, where a “0” or a
“1” results in the same behavior.
means that when the signal is asserted (based on the name of the signal) it is in an electrical low
state. Otherwise, signals are driven in an electrical high state when they are asserted. In state
machine diagrams, a signal name in a condition indicates the condition of that signal being
asserted. If the signal name is preceded by a “!” symbol, then it indicates the condition of that
signal not being asserted. For example, the condition “!STPCLK# and HS” is equivalent to “the
active low signal STPCLK# is unasserted (i.e., it is at 1.5V) and the HS condition is true.” The
symbols “L” and “H” refer respectively to electrical low and electrical high signal levels. The
symbols “0” and “1” refer respectively to logical low and logical high signal levels. For example,
BD[3:0] = “1010” = “HLHL” refers to a hexadecimal “A,” and D[3:0]# = “1010” = “LHLH” also
refers to a hexadecimal “A.” The symbol “X” refers to a “Don’t Care” condition, where a “0” or a
“1” results in the same behavior.