Intel ULV 383 LE80536VC0011M Data Sheet

 Datasheet 

 

283654-003 

16 

The processor can be reset by the RESET# signal while in the Sleep state. If RESET# is driven 
active while the processor is in the Sleep state then SLP# and STPCLK# must immediately be 
driven inactive to ensure that the processor correctly initializes itself. 

Input signals (other than RESET#) may not change while the processor is in the Sleep state or 
transitioning into or out of the Sleep state. Input signal changes at these times will cause 
unpredictable behavior. Thus, the processor is incapable of snooping or latching any events in the 
Sleep state.  

While in the Sleep state, the processor can enter its lowest power state, the Deep Sleep state. 
Removing the processor’s input clock puts the processor in the Deep Sleep state. PICCLK may be 
removed in the Sleep state. 

The Deep Sleep state is the lowest power mode the processor can enter while maintaining its 
context. The Deep Sleep state is entered by stopping the BCLK input to the processor, while it is 
in the Sleep or Quick Start state. For proper operation, the BCLK input should be stopped in the 
Low state. 

The processor will return to the Sleep or Quick Start state from the Deep Sleep state when the 
BCLK input is restarted. Due to the PLL lock latency, there is a delay of up to 30 

µ

sec after the 

clocks have started before this state transition happens. PICCLK may be removed in the Deep 
Sleep state. PICCLK should be designed to turn on when BCLK turns on when transitioning out of 
the Deep Sleep state. 

The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except 
that RESET# assertion will result in unpredictable behavior. 

Normal N/A 

Yes 

Normal 

program 

execution 

Auto Halt 

Approximately 10 bus clocks 

Yes 

S/W controlled entry idle mode 

Stop Grant 

10 bus clocks 

Yes 

H/W controlled entry/exit mobile throttling 

Quick Start 

Through snoop, to HALT/Grant 
Snoop state: immediate  
 
Through STPCLK#, to Normal 
state: 8 bus clocks 

 

Yes 

 

H/W controlled entry/exit mobile throttling 

HALT/Grant 
Snoop 

A few bus clocks after the end 
of snoop activity 

Yes 

Supports snooping in the low power states 

Sleep 

To Stop Grant state 10 bus 
clocks 

No 

H/W controlled entry/exit desktop idle mode 
support 

Deep Sleep 

30 

µ

sec 

No 

H/W controlled entry/exit mobile powered-on 
suspend support 

See Table 32 for power dissipation in the low-power states. 

There are a number of architectural features of the mobile Intel Celeron processor that do not 
function in the Quick Start or Sleep state as they do in the Stop Grant state. The time-stamp