Intel 1.30 GHz YA80543KC0133M User Manual

15

This chapter describes the electrical specifications of the Itanium 2 processor.

Most Itanium 2 processor signals use the Itanium processor’s assisted gunning transceiver logic 
(AGTL+) signaling technology. The termination voltage, V

CTERM

, is generated on the baseboard 

and is the system bus high reference voltage. The buffers that drive most of the system bus signals 
on the Itanium 2 processor are actively driven to V

CTERM

 during a low-to-high transition to 

improve rise times and reduce noise. These signals should still be considered open-drain and 
require termination to V

CTERM

, which provides the high level. The Itanium 2 processor system bus 

is terminated to V

CTERM

 at each end of the bus. There is also support of off-die termination in 

which case the termination is provided by external resistors connected to V

CTERM

.

AGTL+ inputs use differential receivers which require a reference signal (V

REF

). V

REF

 is used by 

the receivers to determine if a signal is a logical 0 or a logical 1. The Itanium 2 processor generates 
V

REF

 on-die, thereby eliminating the need for an off-chip reference voltage source.

VCTERM (1.2 V) input pins on the Itanium 2 processor provide power to the driver buffers and 
on-die termination. The GND pins, in addition to the GND

 

input at the power tab connector, 

provide ground to the processor. Power for the processor core is provided through the power tab 
connector by V

CC,PS

. The 3.3 V pin is included on the processor to provide power to the system 

management bus (SMBus). The V

CTERM

, 3.3 V, and GND pins must remain electrically separated 

from each other.

All pins designated as “N/C” or “No Connect” must remain unconnected. 

 contains Itanium 2 processor system bus signals that have been combined into groups by 

buffer type and whether they are inputs, outputs or bidirectional with respect to the processor.