Intel 1.30 GHz YA80543KC0133M User Manual
Product codes
YA80543KC0133M
20
Datasheet
Electrical Specifications
through
list the AC specifications for the Itanium 2 processor’s clock and
SMBus (timing diagrams begin with
). The Itanium 2 processor uses a differential HSTL
clocking scheme with a frequency of 200, 266 or 333 MHz. The SMBus is a subset of the I2C*
interface which supports operation of up to 100 kHz.
interface which supports operation of up to 100 kHz.
Table 2-8. SMBus DC Specifications
Symbol
Parameter
Minimum
Typ
Maximum
Unit
Notes
3.3V
V
CC
for the System Management
Components
3.14
3.3
3.47
V
3.3V ±5%
V
IL
Input Low Voltage
–0.3
0.3*3.3V
V
V
IH
Input High Voltage
2.31
3.47
V
Max =
3.3 +5%
Min +
0.7*3.3V
V
OL
Output Low Voltage
0.4
V
I
3.3V
3.3V Supply Current
5.0
30.0
mA
I
OL
Output Low Current
3
mA
1
NOTES:
1. The value specified for I
OL
applies to all signals except for THRMALERT#.
I
OL2
Output Low Current
6
mA
2
2. The value specified for I
OL2
applies only to THRMALERT# which is an open drain signal.
I
LI
Input Leakage Current
10
µA
I
LO
Output Leakage Current
10
µA
Table 2-9. LVTTL Signal DC Specifications
Symbol
Parameter
Minimum
Maximum
Unit
Notes
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.0
3.63
V
V
OL
Output Low Voltage
0.4
V
V
OH
Output High Voltage
2.4
V
Table 2-10. System Bus Clock Differential HSTL AC Specifications (Sheet 1 of 2)
Symbol
Parameter
System
Bus
Clock
(MHz)
(MHz)
Minimum
Typ
Maximum
Unit
Figure
Notes
T
period
BCLKp
Period
200
5.0
ns
T
skew
System Clock Skew
200
100
ps
1
f
BCLK
BCLKp Frequency
200
200
200
MHz
2
T
jitter
BCLKp Input Jitter
200
100
ps
3
T
high
BCLKp High Time
200
2.25
2.5
2.75
ns
4
T
low
BCLKp Low Time
200
2.25
2.5
2.75
ns
T
period
BCLKp
Period
266
3.75
ns
T
skew
System Clock Skew
266
60
ps
5
f
BCLK
BCLKp Frequency
266
266
266
MHz
T
jitter
BCLKp Input Jitter
266
50
ps
T
high
BCLKp High Time
266
1.69
1.88
2.06
ns