Intel i7-3517U AV8063801057605 User Manual
Product codes
AV8063801057605
Datasheet, Volume 1
13
Introduction
to transmit data across this interface. This also does not account for packet
overhead and link maintenance.
overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2
• Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per
pair of 984 MB/s using 128b/130b encoding to transmit data across this interface.
This also does not account for packet overhead and link maintenance.
This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 16 GB/s in each direction
simultaneously, for an aggregate of 32 GB/s when x16 Gen 3
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
— DMI -> PCI Express* Port 0
• 64-bit downstream address format; however, the processor never generates an
address above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format; however, the processor responds to upstream
read transactions to addresses above 64 GB (addresses where any of Bits 63:36
are nonzero) with an Unsupported Request response. Upstream write transactions
to addresses above 64 GB will be dropped.
are nonzero) with an Unsupported Request response. Upstream write transactions
to addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
• PCI Express* reference clock is 100-MHz differential clock
• Power Management Event (PME) functions
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
• Power Management Event (PME) functions
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
Note:
The processor does not support PCI Express* Hot-Plug.