Intel i5-3320M AV8063801031900 User Manual

Product codes

AV8063801031900

Datasheet, Volume 1

Power Management

Entry and exit of the C-States at the thread and core level are shown in

While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.

Note:

If enabled, the core C-state will be C1E if all enabled cores have also resolved a core C1 state or higher.

Figure 4-2. Idle Power Management Breakdown of the Processor Cores

Processor Package State

Core 1 State

Thread 1

Thread 0

Core 0 State

Thread 1

Thread 0

Figure 4-3. Thread and Core C-State Entry and Exit

C1E

MWAIT(C1), HLT

MWAIT(C6),

P_LVL3 I/O Read

MWAIT(C3),

P_LV2 I/O Read

MWAIT(C1), HLT

(C1E Enabled)

Table 4-8.

Coordination of Thread Power States at the Core Level

Processor Core

C-State

Thread 1

Thread 0