Intel i5-2450M AV8062700995805 Data Sheet

When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,

the processor core flushes pending cycles and then enters SDRAM ranks that are not

used by Intel graphics memory into self-refresh. The CKE signals remain LOW so the

SDRAM devices perform self-refresh.

The target behavior is to enter self-refresh for package C3 or deeper power states as

long as there are no memory requests to service. The target usage is shown in the

following table.

C0, C1, C1E

Dynamic memory rank power-down based on

idle conditions.

Dynamic memory rank power-down based on

idle conditions.

C3, C6, C7

If the processor graphics engine is idle and

there are no pending display requests, then

enter self-refresh. Otherwise, use dynamic

memory rank power-down based on idle

conditions.

If there are no memory requests, then enter

self-refresh. Otherwise, use dynamic memory

rank power-down based on idle conditions.

S3

Self-Refresh Mode

Self-Refresh Mode

S4

Memory power-down (contents lost)

Memory power-down (contents lost)

Dynamic power-down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The IMC implements

aggressive CKE control to dynamically put the DRAM devices in a power-down state.

The processor core controller can be configured to put the devices in active power-

down (CKE de-assertion with open pages) or pre-charge power-down (CKE de-

assertion with all pages closed). Pre-charge power-down provides greater power

savings, but has a bigger performance impact since all pages will first be closed before

putting the devices in power-down mode.

If dynamic power-down is enabled, all ranks are powered up before doing a refresh

cycle and all ranks are powered down at the end of refresh.

Unused signals should be disabled to save power and reduce electromagnetic

interference. This includes all signals associated with an unused memory channel.

Clocks, CKE, ODE, and CS signals are controlled per DIMM rank and will be powered

down for unused ranks.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the

input receiver (differential sense-amp) should be disabled, and any DLL circuitry

related ONLY to unused signals should be disabled. The input path must be gated to

prevent spurious results due to noise on the unused signals (typically handled

automatically when input receiver is disabled).

The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the

processor is at C3 or deeper power state.

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

March 2015

Datasheet – Volume 1 of 2

Order No.: 330834-004v1

57