Intel i5-2450M AV8062700995805 Data Sheet

SA_RAS#, SB_RAS#

RAS: These signals are used with CAS# and WE# to define

the command being entered.

O

SA_CAS#, SB_CAS#

CAS: These signals are used with RAS# and WE# to define

the command being entered.

O

SA_DQS[7:0]/

SA_DQS#[7:0]

SB_DQS[7:0]/

SB_DQS#[7:0]

Data Strobes: DQS and its complement DQS# signal make

up a differential strobe pair. The data is captured at the

crossing point of DQS and DQS# during read and write

transactions.

I/O

SA_DQ[63:0],

SB_DQ[63:0]

Data Bus: Read and Write Input/Output data signals

I/O

SA_CS#[1:0],

SB_CS#[1:0]

Chip Select : These signals are used to select components

during the active state. There is one Chip Select for each

DRAM rank.

O

SA_CKE[1:0],

SB_CKE[1:0]

Clock Enable: These signals are used to initialize and power

state components. There is one CKE for each DRAM rank.

O

SA_ODT[0], SB_ODT[0]

On Die Termination: Active Termination Control.

O

SM_DRAMRRST#

DRAM RESET: System Memory DRAM Device Reset.

O

VREF_DQ_A, VREF_DQ_B

Data Reference Voltage: Data Signal Reference Voltage.

O

VREF_CA

Command/Address Reference Voltage: Command and

Address Signal Reference Voltage.

O

SA_CK[1:0]/SA_CK#[1:0]
SB_CK[1:0]/SB_CK#[1:0]

Clocks: CK and its complement CK# signal make up a

differential clock pair. The crossing of the positive edge of CK

and the negative edge of its complement CK# are used to

sample the command and control signals.

O

SA_CAA[9:0],

SA_CAB[9:0]
SB_CAA[9:0],

SB_CAB[9:0]

Command Address: These signals are used to provide the

multiplexed command and address.

O

SA_DQS[7:0]/

SA_DQS#[7:0]

SB_DQS[7:0]/

SB_DQS#[7:0]

Data Strobes: DQS and its complement DQS# signal make

up a differential strobe pair. The data is captured at the

crossing point of DQS and DQS# during read and write

transactions.

I/O

SA_DQ[63:0],

SB_DQ[63:0]

Data Bus: Read and Write Input/Output data signals.

I/O

SA_CS#[1:0],

SB_CS#[1:0]

Chip Select : These signals are used to select components

during the active state. There is one Chip Select for each

DRAM rank.

O

SA_CKE[3:0],

SB_CKE[3:0]

Clock Enable: These signals are used to initialize and power

state components. There is one CKE for each DRAM rank.

O

SA_ODT[0], SB_ODT[0]

On Die Termination: Active Termination Control.

O

VREF_DQ_A, VREF_DQ_B

Data Reference Voltage: Data Signal Reference Voltage.

O

VREF_CA

Command/Address Reference Voltage: Command and

Address Signal Reference Voltage.

O

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

March 2015

Datasheet – Volume 1 of 2

Order No.: 330834-004v1

73