Intel D2500 DF8064101055400 Data Sheet

112

Datasheet - Volume 1 of 2

Unused signals should be disabled to save power and reduce electromagnetic 

interference. This includes all signals associated with an unused memory channel. 

Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-

DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the 

input receiver (differential sense-amp) should be disabled, and any DLL circuitry 

related ONLY to unused signals should be disabled. The input path must be gated to 

prevent spurious results due to noise on the unused signals (typically handled 

automatically when input receiver is disabled). 

•

Active power management support using L0s, and L1 states.

•

All inputs and outputs disabled in L2/L3 Ready state.

When STPCLK# pin is asserted, each thread of the processor cores enter the Stop-

Grant state within 1384 bus clocks after the response phase of the processor-issued 

Stop-Grant Acknowledge special bus cycle. When the STPCLK# pin is deasserted, the 

core returns to its previous low-power state.

RSTIN# causes the processor core to immediately initialize itself, but the processor 

core will stay in Stop-Grant state. When RSTIN# is asserted by the system, the 

STPCLK#, DPSLP#, and DPRSTP# pins must be de-asserted prior to RSTIN# 

deassertion as per AC Specification.

While in Stop-Grant state, the processor core will service snoops and latch interrupts 

delivered on the internal bus. The processor core will latch SMI#, INIT# and LINT[1:0] 

interrupts and will service only one of each upon return to the Normal state.

The PBE# (FERR#) signal may be driven when the processor core is in Stop-Grant 

state. PBE# will be asserted if there is any pending interrupt or Monitor event latched 

within the processor core. Pending interrupts that are blocked by the EFLAGS. IF bit 

being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system 

logic that the entire processor core should return to the Normal state.

A transition to the Stop-Grant Snoop state occurs when the processor core detects a 

snoop on the internal bus.