Intel D2500 DF8064101055400 Data Sheet

48

Datasheet - Volume 1 of 2

All data and specifications for DDR3/DDR3L in this chapter are based on post-silicon/ 

validation data. These specifications will be updated with characterized data from 

silicon measurements in the later version of the EDS spec document.

This chapter contains signal group descriptions, absolute maximum ratings, voltage 

identification and power sequencing. The chapter also includes DC and AC 

specifications, including timing diagrams.

The processor has V

CC

 and V

SS 

(ground) inputs for on-chip power distribution. All 

power balls must be connected to their respective processor power planes, while all V

SS

 

balls must be connected to the system ground plane. Use of multiple power and ground 

planes is recommended to reduce I*R drop. The V

CC

 balls must be supplied with the 

voltage determined by the processor Voltage IDentification (VID) signals.

Due to its large number of transistors and high internal clock speeds, the processor is 

capable of generating large current swings between low and full-power states. This 

may cause voltages on power planes to sag below their minimum values, if bulk 

decoupling is not adequate. Larger bulk storage (C

BULK

), such as electrolytic capacitors, 

supply current during longer lasting changes in current demand (for example, coming 

out of an idle condition). Similarly, capacitors act as a storage well for current when 

entering an idle condition from a running condition. To keep voltages within 

specification, output decoupling must be properly designed.

Design the board to ensure that the voltage provided to the processor remains within 

the specifications. Failure to do so can result in timing violations or reduced lifetime of 

the processor. For further information and design guidelines.

The voltage regulator solution needs to provide:

•

Bulk capacitance with low effective series resistance (ESR).

•

A low path impedance from the regulator to the CPU.

•

Bulk decoupling to compensate for large current swings generated during power-

on, or low-power idle state entry/exit.

The power delivery solution must ensure that the voltage and current specifications are 

met, as defined in 

.