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Intel D2500 DF8064101055400 Data Sheet

Product codes
DF8064101055400
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Page of 122
Datasheet - Volume 1 of 2
75
5.1.2
 Loading Specifications
 Loading is 15 lb max static compressive.
5.2
Processor Ballout Assignment
 to 
 are graphic representations of the processor ballout 
assignments. 
 lists the ballout by signal name.
Figure 5-12. Pinmap (Top View, Upper-Left Quadrant)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
---
---
VSS_ N
C TF
VC C AD
M I
---
---
DDI0_
TXN[3
]
---
DPL_ R
EFC LK
N
---
V S S
---
C RT_I
REF
---
---
B
---
VSS_ N
C TF
VSS_ N
C TF
VC C AD
M I
VC C AD
P
---
DDI0_
TXP[3 ]
DDI0 _
AU XN
DPL_ R
EFC LK
P
VSS
C RT_ G
REEN
C RT_R
ED
VC C AD
AC
VSS
---
C
VSS_ N
C TF
VSS_ N
C TF
DDI0 _
TXN[2
]
---
VC C AD
M I
VC C AD
P
VSS
DDI0 _
AUXP
---
DDI1_
AUXN
C RT_ B
LUE
VSS
---
C RT_ V
SYNC
---
D
---
---
---
DDI0_
TXP[2 ]
---
VC C AD
P
---
VSS
VSS
DDI1_
AUXP
---
C RT_ I
RTN
V S S A _C
RTD A C
C RT_ H
SYNC
---
E
VSS_ N
C TF
VSS
---
---
VSS
---
VSS
LVDS_
TXN[1
]
---
LVDS_
IBG
DDI1 _
TXP[0 ]
---
DDI1_
TXN[2
]
---
BREF1
P5
F
---
DDI0 _
TXN[1
]
DDI0 _
TXP[1 ]
VSS
---
---
---
LVDS_
TXP[1 ]
---
LVDS_
VBG
DDI1 _
TXN[0
]
---
DDI1_
TXP[2 ]
---
BREFR
EXT
G
V S S
DDI0 _
TXP[0 ]
DDI0 _
TXN[0
]
---
LVDS_
TXP[3 ]
LVDS_
TXN[3
]
---
VSS
---
LVDS_
TXP[0 ]
V S S
---
V S S
---
V S S
H
---
LV DS _V
RE F H
LVDS_
VREFL
LVDS_
C LKP
V CC A LV
DS
V S S
LVDS_
TXP[2 ]
LVDS_
TXN[2
]
---
LVDS_
TXN[0
]
DDI1 _
TXN[1
]
---
V S S
---
RSVD_
TP_ H1
5
J
VC C DL
VDS
V S S
---
LVDS_
C LKN
---
---
---
---
---
V S S
DDI1 _
TXP[1 ]
---
DDI1_
TXP[3 ]
---
RSVD_
TP_ J1
5
K
---
VC C TH
RM
VSS
VC C AD
M I_ PLL
SFR
DM I_TXN
[0]
DM I_ T
XP[0 ]
V S S
V S S
V S S
---
V S S
---
DDI1_
TXN[3
]
---
V S S
L
V S S
DM I_ R
XN[0 ]
DM I_ R
XP[0 ]
---
DM I_ T
XP[1 ]
DM I_TXN
[1]
V S S
DM I_ T
XN[2 ]
DM I_ T
XP[2 ]
V S S
R S V D_L
11
---
V S S
V S S _CD
V D E T
---
M
---
DM I_ R
XN[1 ]
DM I_ R
XP[1 ]
V S S
---
---
---
---
---
---
---
---
---
---
---
N
DM I_ R
XN[2]
DM I_ R
XP[2 ]
---
V S S
DM I_ T
XP[3 ]
DM I_ T
XN[3 ]
V S S
DM I_RE
F CLK N
DM I_R E
F C LK P
V S S
VC C _
G FX
---
VC C _
G F X
V S S
---
P
---
DM I_ R
XP[3 ]
DM I_ R
XN[3 ]
VSS
---
---
---
---
---
---
VC C _
G FX
---
VC C _
G F X
V S S
---
R
---
---
---
---
RS V D_R
5
RS V D_R
6
RSVD_
TP_ R7
RSVD_
TP_ R8
VC C _
G FX
VC C _
G F X
---
---
---
---
---
T
D M I_RC
O M P
DM I_ R
EF1 P5
VSS
---
---
---
---
---
---
---
VC C _
G FX
---
VC C _
G F X
V S S
---