Intel 807 AV8062701079702 Data Sheet
Product codes
AV8062701079702
Table 12.
DisplayPort and embedded DisplayPort* Resolutions for 1, 2, 4 Lanes – Link
Data Rate of RBR, HBR, and HBR2 for Intel
®
Core
™
M Processor Family
Link Data Rate
Lane Count
1
2
4
RBR
1064x600
1400x1050
2240x1400
HBR
1280x960
1920x1200
2560x1600
HBR2
1920x1200
2880x1800
3200x2000
High-bandwidth Digital Content Protection (HDCP)
HDCP is the technology for protecting high-definition content against unauthorized
copy or unreceptive between a source (computer, digital set top boxes, and so on)
and the sink (panels, monitor, and TVs). The processor supports HDCP 1.4 for content
protection over wired displays (HDMI* and DisplayPort*).
The HDCP 1.4 keys are integrated into the processor and customers are not required
to physically configure or handle the keys.
Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and external components, like Super I/O (SIO) and Embedded
Controllers (EC), to provide processor temperature, Turbo, Configurable TDP, and
memory throttling control mechanisms and many other services. PECI is used for
platform thermal management and real time control and configuration of processor
features and performance.
PECI Bus Architecture
The PECI architecture is based on a wired-OR bus that the clients (as processor PECI)
can pull up high (with strong drive).
The idle state on the bus is near zero.
The following figure demonstrates PECI design and connectivity. While the host/
originator can be a third party PECI host, one of the PECI clients is a processor PECI
device.
2.5
2.5.1
Interfaces—Processor
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
March 2015
Datasheet – Volume 1 of 2
Order No.: 330834-004v1
31