Intel 807 AV8062701079702 Data Sheet

cryptographic applications, such as applications that perform bulk encryption/

decryption, authentication, random number generation, and authenticated encryption.

AES is broadly accepted as the standard for both government and industry

applications, and is widely deployed in various protocols.

Intel AES-NI consists of six Intel SSE instructions. Four instructions, AESENC,

AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption

and decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key

expansion procedure. Together, these instructions provide a full hardware for

supporting AES; offering security, high performance, and a great deal of flexibility.

The processor supports the carry-less multiplication instruction, PCLMULQDQ.

PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the

128-bit carry-less multiplication of two, 64-bit operands without generating and

propagating carries. Carry-less multiplication is an essential processing component of

several cryptographic systems and standards. Hence, accelerating carry-less

multiplication can significantly contribute to achieving high speed secure computing

and communication.

The processor supports Intel

®

 Secure Key (formerly known as Digital Random Number

Generator (DRNG)), a software visible random number generation mechanism

supported by a high quality entropy source. This capability is available to

programmers through the RDRAND instruction. The resultant random number

generation capability is designed to comply with existing industry standards in this

regard (ANSI X9.82 and NIST SP 800-90).

Some possible usages of the RDRAND instruction include cryptographic key generation

as used in a variety of applications, including communication, digital signatures,

secure storage, and so on.

The processor has a RDSEED instruction that enables system software and security

vendors who need to seed or reseed a software PRNG.

The RDSEED instruction will be a companion to the RDRAND instruction. RDSEED,

along with RDRAND, fills out Intel's standards compliant (such as NIST SP800-90 A, B,

and C) Hardware-based Random Number Generator portfolio.

The x2APIC architecture extends the xAPIC architecture that provides key

mechanisms for interrupt delivery. This extension is primarily intended to increase

processor addressability.

Specifically, x2APIC:
•

Retains all key elements of compatibility to the xAPIC architecture:
— Delivery modes
— Interrupt and processor priorities
— Interrupt sources
— Interrupt destination types

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

Datasheet – Volume 1 of 2

March 2015

40

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