Intel 807 AV8062701079702 Data Sheet

waking-up all page-buffers are empty.) The LPDDR does not have a DLL. As a

result, the power savings are as good as PPD/DLL-off, but will have lower exit

latency and higher performance.

The CKE is determined per rank, whenever it is inactive. Each rank has an idle-

counter. The idle-counter starts counting as soon as the rank has no accesses, and if

it expires, the rank may enter power-down while no new transactions to the rank

arrives to queues. The idle-counter begins counting at the last incoming transaction

arrival.

It is important to understand that since the power-down decision is per rank, the IMC

can find many opportunities to power down ranks, even while running memory

intensive applications; the savings are significant (may be few Watts, according to the

DDR specification). This is significant when each channel is populated with more

ranks.

Selection of power modes should be according to power-performance or thermal

trade-offs of a given system:
•

When trying to achieve maximum performance and power or thermal

consideration is not an issue – use no power-down

•

In a system which tries to minimize power-consumption, try using the deepest

power-down mode possible – PPD/DLL-off with a low idle timer value.

•

In high-performance systems with dense packaging (that is, tricky thermal

design) the power-down mode should be considered in order to reduce the heating

and avoid DDR throttling caused by the heating.

The default value that BIOS configures in "PM_PDWN_config_0_0_0_MCHBAR" is

6080h; that is, PPD/DLL-off mode with idle timer of 80h, or 128 DCLKs. This is a

balanced setting with deep power-down mode and moderate idle timer value.

The idle timer expiration count defines the number of DCKLs that a rank is idle that

causes entry to the selected power mode. As this timer is set to a shorter time, the

IMC will have more opportunities to put DDR in power-down. There is no BIOS hook to

set this register. Customers choosing to change the value of this register can do it by

changing it in the BIOS. For experiments, this register can be modified in real time if

BIOS does not lock the IMC registers.

During power-up, CKE is the only input to the SDRAM that has its level recognized

(other than the DDR3L/DDR3L-RS reset pin) once power is applied. It must be driven

LOW by the DDR controller to make sure the SDRAM components float DQ and DQS

during power-up. CKE signals remain LOW (while any reset is active) until the BIOS

writes to a configuration register. Using this method, CKE is ensured to remain

inactive for much longer than the specified 200 micro-seconds after power and clocks

to SDRAM devices are stable.

During S0 idle state, system memory may be conditionally placed into self-refresh

 for more details on conditional self-

refresh with Intel HD Graphics enabled.

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

Datasheet – Volume 1 of 2

March 2015

56

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