Intel 807 AV8062701079702 Data Sheet

The following are the general types of reserved (RSVD) signals and connection

guidelines:
•

RSVD – these signals should not be connected

•

RSVD_TP – these signals should be routed to a test point

Arbitrary connection of these signals to VCC, VDDQ, VSS, or to any other signal

(including each other) may result in component malfunction or incompatibility with

future processors. See 

 on page 72 for a pin listing of the processor

and the location of all reserved signals.

For reliable operation, always connect unused inputs or bi-directional signals to an

appropriate signal level. Unused active high inputs should be connected through a

resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may

interfere with some Test Access Port (TAP) functions, complicate debug probing, and

prevent boundary scan testing. A resistor must be used when tying bi-directional

signals to power or ground. When tying any signal to power or ground, a resistor will

also allow for system testability.

Signals are grouped by buffer type and similar characteristics as listed in the following

table. The buffer type indicates which signaling technology and specifications apply to

the signals. All the differential signals and selected DDR3L / DDR3L-RS / LPDDR3 and

Control Sideband signals have On-Die Termination (ODT) resistors. Some signals do

not have ODT and need to be terminated on the board.

All Control Sideband Asynchronous signals are required to be asserted/de-asserted for

at least 10 BCLKs with maximum Trise/Tfall of 6 ns in order for the processor to

recognize the proper signal state.

Differential

DDR3L/DDR3L-RS

Output

SA_CK[3:0], SA_CK#[3:0], SB_CK[3:0], SB_CK#[3:0]

LPDDR3 Output

SA_CK[1:0], SA_CK#[1:0], SB_CK[1:0], SB_CK#[1:0]

Single ended

DDR3L/DDR3L-RS

Output

SA_MA[15:0], SB_MA[15:0], SA_BS[2:0], SB_BS[2;0],

SA_WE#, SB_WE#, SA_RAS#, SB_RAS#, SA_CAS#, SB_CAS#

LPDDR3 Output

SA_CAA[9:0], SA_CAB[9:0], SB_CAA[9:0], SB_CAB[9:0]

Single ended

DDR3L/DDR3L-RS

Output

SA_CKE[3:0], SB_CKE[3:0], SA_CS#[3:0], SB_CS#[3:0],

SA_ODT[3:0], SB_ODT[3:0]

LPDDR3 Output

SA_CKE[3:0], SB_CKE[3:0], SA_CS#[1:0], SB_CS#[1:0],

SA_ODT0, SB_ODT0

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

March 2015

Datasheet – Volume 1 of 2

Order No.: 330834-004v1

85