Intel 887 AV8062701085401 Data Sheet

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,

the system memory controller continuously monitors pending requests to system

memory for the best use of bandwidth and reduction of latency. If there are multiple

requests to the same open page, these requests would be launched in a back-to-back

manner to make optimum use of the open memory page. This ability to reorder

requests on the fly allows the system memory controller to further reduce latency and

increase bandwidth efficiency.

In all modes, the frequency of system memory is the lowest frequency of all memory

placed in the system, as determined through the SPD registers for the memory.

For systems using DDR3L/DDR3L-RS SO-DIMM modules with different latency

populated across the channels, the BIOS will use the slower of the two latencies for

both channels. For dual-channel mode, both channels must have the SO-DIMM

connector populated. For single-channel mode, only a single channel can have the SO-

DIMM connector be populated.

The system memory controller supports two memory organization modes – single-

channel and dual-channel. Depending on how the DIMM Modules or DRAM Down

Devices are configured in each memory channel, a number of different configurations

can exist.

In this mode, all memory cycles are directed to a single-channel. Single-channel mode

is used when either Channel A or Channel B are populated in any order, but not both.

The system memory controller supports Intel Flex Memory Technology Mode where

memory is divided into a symmetric and asymmetric zone. The symmetric zone starts

at the lowest address in each channel and is contiguous until the asymmetric zone

begins or until the top address of the channel with the smaller capacity is reached. In

this mode, the system runs with one zone of dual-channel mode and one zone of

single-channel mode, simultaneously, across the entire memory array. This mode is

used when both Channel A and Channel B are populated with memory but the total

amount of memory in each channel is not the same.

Channels A and B can be mapped for Physical Channel 0 and 1 respectively or vice

versa; however, the Channel A size must be greater or equal to the Channel B size.

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

March 2015

Datasheet – Volume 1 of 2

Order No.: 330834-004v1

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