Intel E5-1428L CM8062001144000 Data Sheet

V

OL

Output Low Voltage

Varies

10

V

OH

Output High Voltage

V

CCD

R 

ON

DDR4 Clock Buffer
On Resistance

27

33

ohm

6

R 

ON

DDR4 Command Buffer
On Resistance

16

20

ohm

6

R 

ON

DDR4 Reset Buffer
On Resistance

78

ohm

6

V

OL_CMOS1.2V

Output Low
Voltage, Signals
DDR_RESET_ C{01/23}_N

0.2*V

CCD

V

1, 2

V 

OH_CMOS1.2V

Output High
Voltage, Signals
DDR_RESET_ C{01/23}_N

0.9*V

CCD

V

1, 2

R 

ON

DDR4 Control Buffer
On Resistance

27

33

ohm

6

ALERT_N

On-Die Termination
for Parity Error Signals

81

90

99

ohm

V

IL

Input Low Voltage
DRAM_PWR_OK_C{01/23}

304

mV

2, 3

V

IH

Input High Voltage
DRAM_PWR_OK_C{01/23}

800

mV

2, 4, 5

Note: 
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The voltage rail V

CCD

 which will be set to 1.2V nominal depending on the voltage of all DIMMs connected to the processor.

3. V

IL

 is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.

4. V

IH

 is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.

5. V

IH

 and V

OH

 may experience excursions above V

CCD

. However, input signal drivers must comply with the signal quality

specifications. Refer to 

 on page 44.

6. This is the pull down driver resistance. Reset drive does not have a termination.
7. R

VTT_TERM

 is the termination on the DIMM and not controlled by the processor. Refer to the applicable DIMM datasheet.

8. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
9. Input leakage current is specified for all DDR4 signals.
10.Vol = Ron * [VCCD/(Ron + Rtt_Eff)], where Rtt_Eff is the effective pull-up resistance of all DIMMs in the system, including

ODTs and series resistors on the DIMMs.

Intel

®

 Xeon

®

 Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical

September 2014

Datasheet

Order No.: 330783-001

37