Intel E5-1428L CM8062001144000 Data Sheet

This chapter describes the Intel

®

 Xeon

®

 processor E5-1600 and E5-2600 v3 product

families signals. They are arranged in functional groups according to their associated

interface or category.

DDR{0/1/2/3}_ACT_N

Activate. When asserted, indicates MA[16:14] are command signals

(RAS_N, CAS_N, WE_N).

DDR{0/1/2/3}_ALERT_N

Parity Error detected by the DIMM (one for each channel).

DDR{0/1/2/3}_BA[1:0]

Bank Address. Defines which bank is the destination for the current

Activate, Read, Write, or Precharge command.

DDR{0/1/2/3}_BG[1:0]

Bank Group: Defines which bank group is the destination for the current

Active, Read, Write or Precharge command. BG0 also determines which

mode register is to be accessed during a MRS cycle.

DDR{0/1/2/3}_CAS_N

Column Address Strobe. MUXed with DDR{0/1/2/3}_MA[15].

DDR{0/1/2/3}_CID[4:0]

Chip ID. Used to select a single die out of the stack of a 3DS device.
CID[4:3] are MUXed with CS_N[7:6], respectively.
CID[1:0] are MUXed with CS_N[3:2], respectively.

DDR{0/1/2/3}_CKE[5:0]

Clock Enable.

DDR{0/1/2/3}_CLK_DN[3:0]
DDR{0/1/2/3}_CLK_DP[3:0]

Differential clocks to the DIMM. All command and control signals are valid

on the rising edge of clock.

DDR{0/1/2/3}_CS_N[9:0]

Chip Select. Each signal selects one rank as the target of the command and

address.
CS_N[7:6] are MUXed with CID[4:3], respectively.
CS_N[3:2] are MUXed with CID[1:0], respectively.

DDR{0/1/2/3}_DQ[63:0]

Data Bus. DDR4 Data bits.

DDR{0/1/2/3}_DQS_DP[17:0]
DDR{0/1/2/3}_DQS_DN[17:0]

Data strobes. Differential pair, Data/ECC Strobe. Differential strobes latch

data/ECC for each DRAM. Different numbers of strobes are used depending

on whether the connected DRAMs are x4,x8. Driven with edges in center of

data, receive edges are aligned with data edges.

DDR{0/1/2/3}_ECC[7:0]

Check bits. An error correction code is driven along with data on these lines

for DIMMs that support that capability

DDR{0/1/2/3}_MA[17:0]

Memory Address. Selects the Row address for Reads and writes, and the

column address for activates. Also used to set values for DRAM

configuration registers. MA[16], MA[15], and MA[14] are MUXed with

RAS_N, CAS_N, and WE_N, respectively.

DDR{0/1/2/3}_PAR

Even parity across Address and Command.

Intel

®

 Xeon

®

 Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical

September 2014

Datasheet

Order No.: 330783-001

49