Intel E5-1428L CM8062001144000 Data Sheet

1 = Default. The platform is Intel TXT enabled. All sockets should be set to

one. In a non-Scalable DP platform this is the default. When this is set,

Intel TXT functionality requires user to explicitly enable Intel TXT via BIOS

setup.
This signal is pulled up on the die, refer to 

on page 26 for details.

V

CCIN

Input to the Integrated Voltage Regulator (IVR) for the processor cores,

lowest level caches (LLC), ring interface, PLL, IO, and home agent. It is

provided by a VR 12.5 compliant motherboard voltage regulator (MBVR) for

each CPU socket. The output voltage of this MBVR is controlled by the

processor, using the serial voltage ID (SVID) bus.

V

CCIN_SENSE

V

SS_VCCIN_SENSE

V

CCIN_SENSE

 and V

SS_VCCIN_SENSE

 are remote sense signals for V

CCIN

MBVR12.5 and are used by the voltage regulator to ensure accurate

voltage regulation. These signals must be connected to the voltage

regulator feedback circuit, which ensures the output voltage remains within

specification.

V

CCD_01

V

CCD_23

Fixed 1.2V power supply for the processor system memory interface.

Provided by two MBVR 12.0 or 12.5 compliant regulators per CPU socket.

V

CCD_01

 and V

CCD_23

 are used for memory channels 0 &1 and 2 & 3,

respectively. The valid voltage of this supply (1.20V) is configured by BIOS

after determining the operating voltages of the installed memory. V

CCD_01

and V

CCD_23

 will also be referred to as V

CCD

.

Note: The processor must be provided V

CCD_01

 and V

CCD_23

 for proper

operation, even in configurations where no memory is populated. A

MBVR 12.0 or 12.5 controller is required.

V

SS

Processor ground return.

V

CCIO_IN

IO voltage supply input.

V

CCPECI

Power supply for PECI.

Intel

®

 Xeon

®

 Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical

September 2014

Datasheet

Order No.: 330783-001

57