Intel i5-2435M AV8062700995706 Data Sheet

Any system memory (SM) interface signal that goes to a memory in which it is not

connected to any actual memory devices is tri-stated. The benefits of disabling unused

SM signals are:
•

Reduced power consumption.

•

Reduced possible overshoot/undershoot signal quality issues seen by the

processor I/O buffer receivers caused by reflections from potentially un-

terminated transmission lines.

When a given rank is not populated, the corresponding chip select and CKE signals are

not driven.

At reset, all rows must be assumed to be populated, until it can be determined that

the rows are not populated. This is due to the fact that when CKE is tri-stated with

DRAMs present, the DRAMs are not ensured to maintain data integrity. CKE tri-state

should be enabled by BIOS where appropriate, since at reset all rows must be

assumed to be populated.

CKE tri-state should be enabled by BIOS where appropriate, since at reset all rows

must be assumed to be populated.

The processor implements extensive support for power management on the memory

interface.The processor drives four CKE pins, one per rank.

The CKE is one of the power save means. When CKE is off, the internal DDR clock is

disabled and the DDR power is reduced. The power saving differs according to the

selected mode and the DDR type used. For more information, refer to the IDD table in

the DDR specification.

The processor supports four different types of power-down modes in package C0. The

different power-down modes can be enabled through configuring

"PM_PDWN_config_0_0_0_MCHBAR". The type of CKE power-down can be configured

through PDWN_mode (bits 15:12) and the idle timer can be configured through

PDWN_idle_counter (bits 11:0). The different power-down modes supported are:
•

No power-down (CKE disable)

•

Active power-down (APD): This mode is entered if there are open pages when

de-asserting CKE. In this mode the open pages are retained. Power-saving in this

mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this

mode is defined by tXP – small number of cycles. For this mode, DRAM DLL must

be on.

•

PPD/DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this

mode is the best among all power modes. Power consumption is defined by

IDD2P1. Exiting this mode is defined by tXP, but also tXPDLL (10–20 according to

DDR type) cycles until first data transfer is allowed. For this mode, DRAM DLL

must be off.

•

Pre-charged power-down (PPD): This mode is entered if all banks in DDR are

pre-charged when de-asserting CKE. Power saving in this mode is intermediate –

better than APD, but less than DLL-off. Power consumption is defined by IDD2P1.

Exiting this mode is defined by tXP. The difference from APD mode is that when

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

March 2015

Datasheet – Volume 1 of 2

Order No.: 330834-004v1

55