Intel i5-2435M AV8062700995706 Data Sheet

PROCPWRGD

The processor requires this input signal to be a clean

indication that the V

CC

 and V

DDQ

 power supplies are

stable and within specifications. This requirement

applies regardless of the S-state of the processor.

'Clean' implies that the signal will remain low (capable

of sinking leakage current), without glitches, from the

time that the power supplies are turned on until the

supplies come within specification. The signal must

then transition monotonically to a high state.

I

Asynchronous CMOS

VCCST_PWRGD

The processor requires this input signal to be a clean

indication that the V

CCST

 and V

DDQ

 power supplies are

stable and within specifications. This single must have

a valid level during both S0 and S3 power states.

'Clean' implies that the signal will remain low (capable

of sinking leakage current), without glitches, from the

time that the power supplies are turned on until the

supplies come within specification. The signal must

then transition monotonically to a high state."

I

Asynchronous CMOS

PROC_DETECT#

Processor Detect: This signal is pulled down directly

(0 Ohms) on the processor package to ground. There

is no connection to the processor silicon for this signal.

System board designers may use this signal to

determine if the processor is present.

—

VCC

Processor main power rail.

Ref

VDDQ

Processor I/O supply voltage for DDR3L/DDR3L-RS/

LPDDR3.

Ref

VCCST

Sustain voltage for the processor in standby modes

Ref

VIDSOUT
VIDSCLK
VIDALERT#

VIDALERT#, VIDSCLK, and VIDSCLK comprise a three

signal serial synchronous interface used to transfer

power management information between the

processor and the voltage regulator controllers.

I/O CMOS

O CMOS

I CMOS

VR_EN

Sideband output from the processor which controls

disabling of the VR when the processor is in the C10

state. This signal will be used to disable the VR only if

the processor is configured to support VR disabling

using VR_CURRENT_CONFIG MSR (601h).

O

VR Enable CMOS

VR_READY

Sideband signal which indicates to the processor that

the external voltage regulator for the V

CC

 power rail is

valid.

I

CMOS

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

March 2015

Datasheet – Volume 1 of 2

Order No.: 330834-004v1

77