Intel 9550 CM8063101049807 Data Sheet
Product codes
CM8063101049807
Introduction
14
Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet
The Intel
®
Itanium
®
Processor 9500 Series delivers increased levels of flexibility,
reliability, performance, and cost-effective scalability for your most data-intensive
business and technical applications.
business and technical applications.
The Intel
®
Itanium
®
Processor 9500 Series processor provides up to 32 megabytes LLC
cache, Hyper-Threading Technology for increased performance, Intel
®
Virtualization
Technology for improved virtualization, Intel
®
Cache Safe Technology for increased
availability. Intel
®
Turbo Boost Technology, featuring sustained boost. The Intel
®
Itanium
®
Processor 9500 Series employs advanced power monitoring and control to
deliver a higher processor frequency at all times, for maximum performance on all
workloads. The result is a higher thermal envelope utilization for more overall
performance. The Intel
workloads. The result is a higher thermal envelope utilization for more overall
performance. The Intel
®
Itanium
®
Processor 9500 Series offers large cache arrays
covered by ECC including the large LLC utilizing double correct/triple detect (DECTED)
and protecting the MLI/MLD with in-line single correct/double detect (SECDED). In
addition, the processor provides extensive parity protection and parity interleaving on
nearly all RFs, end-to-end parity protection with recovery-support on all critical internal
buses and data paths including the ring. Residue protection on Floating Point unit,
along with the adoption of radiation-hardened (RAD) sequential latching elements for
vulnerable architectural and state. The Intel
and protecting the MLI/MLD with in-line single correct/double detect (SECDED). In
addition, the processor provides extensive parity protection and parity interleaving on
nearly all RFs, end-to-end parity protection with recovery-support on all critical internal
buses and data paths including the ring. Residue protection on Floating Point unit,
along with the adoption of radiation-hardened (RAD) sequential latching elements for
vulnerable architectural and state. The Intel
®
Itanium
®
Processor 9500 Series
processor interfaces exclusively with the Ararat II Voltage Regulator Module.
The Intel
®
Itanium
®
Processor 9500 Series consists of up to 8 core processors and a
system interface unit. Each processor core provides a 12-wide, 11-stage deep
execution pipeline. The resources consist of six integer units, one integer multiply unit,
four multimedia units, two load/store units, three branch units and two floating-point
units each capable of extended, double and single precision arithmetic. The hardware
employs dynamic prefetch, branch prediction, a register scoreboard, and non-blocking
caches to optimize for compile-time non-determinism. 32 additional stacked general
registers are provided over the Intel
execution pipeline. The resources consist of six integer units, one integer multiply unit,
four multimedia units, two load/store units, three branch units and two floating-point
units each capable of extended, double and single precision arithmetic. The hardware
employs dynamic prefetch, branch prediction, a register scoreboard, and non-blocking
caches to optimize for compile-time non-determinism. 32 additional stacked general
registers are provided over the Intel
®
Itanium
®
Processor 9300 Series, and hardware
support is provided for denormal, unnormal, and pseudo-normal operands for floating
point software assist offloading.
point software assist offloading.
New instructions on the Intel
®
Itanium
®
Processor 9500 Series simplify common tasks.
They include: clz (count leading zeros), mpy4 and mpyshl4(unsigned integer multiply/
shift and multiply), mov-to-DAHR/mv-from-DAHR (for improved MLD/FLD prefetcher
hinting and performance), and hint@priority (used by the processor to temporarily
allocate more resources to a thread). Advanced Explicitly Parallel Instruction
Computing (EPIC) is enhanced on the Intel
shift and multiply), mov-to-DAHR/mv-from-DAHR (for improved MLD/FLD prefetcher
hinting and performance), and hint@priority (used by the processor to temporarily
allocate more resources to a thread). Advanced Explicitly Parallel Instruction
Computing (EPIC) is enhanced on the Intel
®
Itanium
®
Processor 9500 Series by
increasing the capacity of retiring instructions per cycle from 6 to a maximum of 12
instructions per cycle per core.
instructions per cycle per core.
Intel
®
Hyper-threading Technology is enhanced in the Intel
®
Itanium
®
Processor 9500
Series with dual domain multithreading, which enables independent front-end and
back-end pipeline execution to improve multi-thread efficiency and performance for
both new and legacy applications. It provides hardware support for two threads per
core, with a threaded 96 entry per thread Instruction Buffer and threaded MLDTLB and
FLDTLB, and a dedicated load return path from the MLD to the integer register file.
Three levels of on-die cache minimize overall memory latency, with 16 KB instruction
cache FLI/16 KB write-through data cache FLD that comprise the FLC and 512 KB MLI/
256 KB writeback data cache MLD that comprise the MLC.
back-end pipeline execution to improve multi-thread efficiency and performance for
both new and legacy applications. It provides hardware support for two threads per
core, with a threaded 96 entry per thread Instruction Buffer and threaded MLDTLB and
FLDTLB, and a dedicated load return path from the MLD to the integer register file.
Three levels of on-die cache minimize overall memory latency, with 16 KB instruction
cache FLI/16 KB write-through data cache FLD that comprise the FLC and 512 KB MLI/
256 KB writeback data cache MLD that comprise the MLC.
The Intel
®
Itanium
®
Processor 9500 Series offers a new RAS feature: Intel
®
Instruction Replay Technology. Pipeline replay resolves stall conditions that occur when
the microprocessor pipeline encounters a resource hazard that prevents immediate
execution. In a replay, the instruction that encountered the resource hazard is removed
from the pipeline, along with all the instructions that come after it. The instruction is
then read again out of the instruction buffer for replay and re-executed. To ensure a
the microprocessor pipeline encounters a resource hazard that prevents immediate
execution. In a replay, the instruction that encountered the resource hazard is removed
from the pipeline, along with all the instructions that come after it. The instruction is
then read again out of the instruction buffer for replay and re-executed. To ensure a