Intel 9550 CM8063101049807 Data Sheet

Product codes

CM8063101049807

Intel

Itanium

Processor 9300 Series and 9500 Series Datasheet

143

System Management Bus Interface

System Management Bus

Interface

The Intel

Itanium

Processor 9300 Series and Intel

Itanium

Processor 9500 Series

package includes a system management bus (SMBus) interface. This chapter describes
the features of the SMBus and its components.

6.1

Introduction

The Intel

Itanium

Processor 9300 Series and Intel

Itanium

Processor 9500 Series

package includes an SMBus interface which allows access to a memory component
subdivided into two sections (referred to as the PIROM and the Scratch EEPROM), and
sideband access to the processor’s control & status registers (CSRs). This chapter is
devoted to the PIROM field definitions of the memory component. For details of SMBus
transactions used to access processor Control and Status Registers (CSRs), refer to the
RS - Intel

Itanium

9300 Processor External Design Specification or the RS - Intel

Itanium

Processor 9500 Series External Design Specification.

The PIROM consists of the following sections:

• General
• Processor
• Processor Core
• Processor Uncore
• Cache
• Package
• Part Number
• Thermal Reference
• Feature
• Other

Details on each of these sections are described in

Section 6.4

The processor SMBus implementation uses the clock and data signals of the System
Management Bus (SMBus) Specification. Layout and routing guidelines are available in
the Intel® Itanium® 9300 Series and Intel® Itanium® 9500 Series Platform Design
Guide.