Intel 9550 CM8063101049807 Data Sheet

160

CSI[3:0]R[P/N]Dat[19:0], 

CSI[5:4]R[P/N]Dat[9:0]

I

These input data signals provide means of communication between two ports via 

one uni-directional transfer link (In). The RX links, are terminally ground 

referenced. The ports [3:0] with [19:0] bit lanes can be configured as a full width 

link with all 20 active lanes, a half width link with 10 active lanes or as a quarter 

width link with five active lanes.

Example: CSI4RPDAT[0] represents port 5 Data, lane 0, receive signal and positive 

bit of the differential pair.

CSI[3:0]T[P/N]Dat[19:0], 

CSI[5:4]T[P/N]Dat[9:0]

O

These output data signals provide means of communication between two ports via 

one uni-directional transfer link (Out).The links, Tx, are terminally ground 

referenced. The ports [3:0] with [19:0] bit lanes can be configured as a full width 

link with 20 active lanes, a half width link with 10 active lanes or as a quarter width 

link with five active lanes.

Example: CSI4TPDAT[0] represents port 5 Data, lane 0, transmit signal and 

positive bit of the differential pair.

ERROR[0]_N

O

Side band signaling for system management.
Refer to the Intel

9500 Series Platform Design Guide for pin considerations.

ERROR[1]_N

O

Side band signaling for system management. Assertion on this pin indicates that an 

error reset response is required from the platform.
Refer to the Intel

9500 Series Platform Design Guide for pin considerations.

FBD0NBICLK[A/B][P/N]0 

I

These differential pair clock signals generated from the branch zero, channel A and 

B of FB-DIMMs are input to the processor.

Example: FBD0NBICLKAP0 represents FB-DIMM branch 0, northbound clock input 

signal of channel A and positive bit of the differential pair. 

Interface Name Port 

Number

Receiver

Differential 

Pair
Polarity 

Positive/

Negative

Lane 

Number

Interface Name Port 

Number

Transmitter

Differential 

Pair
Polarity 

Positive/

Negative

Lane 

Number

Interface 

Name

Branch 

Number

North 

Bound

Input

Clock

Channel

Differential 

Pair
Polarity 

Positive/

Negative