Intel 9550 CM8063101049807 Data Sheet

43

The Flexible Motherboard (FMB) guidelines are estimates of the maximum ratings that 
the processor will have over certain time periods. The ratings are only estimates as 
actual specifications for future processors may differ. The processor may or may not 
have specifications equal to the FMB value in the foreseeable future. 

 defines the FMB voltage specification values applied to the 130 W and 

170 W SKUs for the Intel

®

 Itanium

®

 Processor 9500 Series. Current specifications are 

identified for each processor SKU separately in 

. 

CVID

Range

VCCCORE VID Range

0.800

1.105

1.22

V

1

CVID

Boot

VCCCORE VID default value

0

V

1

UVID

Range

VCCUNCORE VID Range

0.800

0.975

1.19

V

1

UVID

Boot

VCCUNCORE VID default value

1.0

V

1

VCCUNCORE

Processor uncore supply voltage

See 

 and 

V

2,  1

1. The voltage specification requirements are measured across the VCCUNCORESENSE and VSSUNCORESENSE pins using an 

oscilloscope set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 mOhms minimum impedance 

at the processor socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from 

the system is not coupled into the scope probe.

VCCCORE

Processor core supply voltage

See 

 and 

V

2,  3,  4

2. These voltages are target only. A variable voltage source should exist on systems in th e event that a different voltage is required. 

See the Ararat II Voltage Regulator Module Design Guide for more information. 

3. Uncore and Core voltage and Current Rating are at the Package Pad.

4. The voltage specification requirements are measured across the VCCCORESENSE and VSSCORESENSE pins using an oscilloscope 

set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 mOhms minimum impedance at the 

processor socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the 

system is not coupled into the scope probe.

VID Transition

VID step size during transition

± 5

mV

VID_DCshift

Total allowable DC load line shift from VID 

steps.

-420

mV

5

5. Warm boot reset, only in downward direction.

VCCIO

Processor I/O supply voltage at die 

including all AC and DC

1.011

1.050

1.094

V

6

6. Min and Max range is spec at the die for VCCIO. This range includes 35 mV p-p AC noise. It also includes any DC and AC 

tolerances at package pin.

VCCIO

Processor I/O supply voltage (high 

frequency AC p-p noise at die)

35

mV

VCCIO

Processor I/O supply voltage at package 

pin including all AC and DC

1.026

1.075

1.088

V

7

VCCA

Processor analog supply voltage (DC spec)

1.764

1.8

1.836

V

8

VCCA

Processor analog supply voltage (AC 

tolerance for noise at scope full 

bandwidth)

1.8

±25

mV

8, 9

VCCA

Processor analog supply voltage (AC 

tolerance for noise > 1MHz)

1.8

±15

mV

9, 10

VCCA

Processor analog supply voltage (Total = 

DC spec + AC tolerance)

1.739

1.8

1.861

V

VCCA Ramp

Min time allowed to ramp VCCA from 10% 

to 90% typical value

1

10

ms

VCC33_SM

3.3 V supply voltage

3.135

3.3

3.465

V