Intel 9550 CM8063101049807 Data Sheet
Product codes
CM8063101049807
Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet
71
Electrical Specifications
2.14
Test Access Port (TAP) Connection
The recommended TAP connectivity is detailed in the Intel
®
Itanium
®
Platform Debug
Port Design Guide (DPDG).
§
T11
RESET_N deasserted delay to SKTID[2]
deasserted (as error in)
100
ns
T12
SKTID[2] (as error in) asserted pulse width
3
SYSCLK
cycles
T13
BOOTMODE[2:0], FLASHROM_CFG[1:0] hold
after RESET_N deasserted
1
us
T14
BOOTMODE[2:)], FLASHROM_CFG[1:0] setup to
RESET_N asserted
0
ns
Table 2-40. RESET_N and SKTID Timing (Sheet 2 of 2)
Parameter
Description
MIN
MAX
UNIT