Intel 9560 CM8063101049716 Data Sheet
Product codes
CM8063101049716
System Management Bus Interface
150
Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet
6.2.3
PIROM and Scratch EEPROM Supported SMBus
Transactions
The PIROM responds to two SMBus packet types: Read Byte and Write Byte. However,
since the PIROM is write-protected, it will acknowledge a Write Byte command but
ignores the data. The Scratch EEPROM responds to Read Byte and Write Byte
commands.
since the PIROM is write-protected, it will acknowledge a Write Byte command but
ignores the data. The Scratch EEPROM responds to Read Byte and Write Byte
commands.
illustrates the Read Byte command.
illustrates the
Write Byte command.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘A’ represents
an acknowledge (ACK), and ‘///’ represents a negative acknowledge (NACK). The
shaded bits are transmitted by the PIROM or Scratch EEPROM, and the bits that aren’t
shaded are transmitted by the SMBus host controller. In the tables, the data addresses
indicate 8 bits.
an acknowledge (ACK), and ‘///’ represents a negative acknowledge (NACK). The
shaded bits are transmitted by the PIROM or Scratch EEPROM, and the bits that aren’t
shaded are transmitted by the SMBus host controller. In the tables, the data addresses
indicate 8 bits.
The SMBus host controller should transmit 8 bits with the most significant bit indicating
which section of the EEPROM is to be addressed: the PIROM (MSB = 0) or the Scratch
EEPROM (MSB = 1).
which section of the EEPROM is to be addressed: the PIROM (MSB = 0) or the Scratch
EEPROM (MSB = 1).
6.3
Memory Component Addressing
The Intel
®
Itanium
®
Processor 9300 Series and Intel
®
Itanium
®
Processor 9500 Series
PIR_A[1:0] pins are used as the memory address selection signals. The processor does
not specify the value on these pins. It is left to the system architect to set the SMBus
memory map. If the processor is the only device on the bus, these pins may be tied to
VSS. PIR_A[2] is tied to VSS internal to the processor.
not specify the value on these pins. It is left to the system architect to set the SMBus
memory map. If the processor is the only device on the bus, these pins may be tied to
VSS. PIR_A[2] is tied to VSS internal to the processor.
shows the address
connections within the processor package.
Table 6-2.Read Byte SMBus Packet
S
Slave
Address
Write
A
Command
Code
A
S
Slave
Address
Read
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Table 6-3.Write Byte SMBus Packet
S
Slave
Address
Write
A
Command
Code
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1