Intel 9560 CM8063101049716 Data Sheet

16

The Intel

®

 Itanium

®

 Processor 9500 Series is an eight core architecture. It supports up 

to eight cores, each with its own First Level Cache (FLC) and Mid Level Cache (MLC), 
both of which are split into instruction and data caches (FLI/FLD and MLI/MLD, 
respectively). The Last Level Cache (LLC) is shared among the cores and supports up to 
32 MB. Also supported are the following page sizes for purges or inserts: 4K, 8K, 16K, 
64K, 256K, 1M, 4M, 16M, 64M, 256M, 1G, 4G.

The architecture interfacing the cores to the system is referred to as the uncore. Each 
Intel

®

 Itanium

®

 Processor 9500 Series core interfaces to the Ring. The Ring provides 

connectivity to the Last Level Cache via the Cache Controllers (Cboxes). The Ring also 
provides connectivity to Intel QPI via Ring/Sbox. The Sbox and Cbox provide the 
supports for the two Intel QPI Caching Agents. The processor has two Home Agents 
(Bbox). The Bbox interfaces between the memory controller and the Intel

®

 QuickPath 

Interconnect and supports a directory cache. Each memory controller supports two 
Intel

®

 Scalable Memory Interconnects (Intel

®

 SMI) in lockstep. The Intel SMI are the 

interconnects to Scalable Memory Buffer. The Intel

®

 Itanium

®

 Processor 9500 Series 

processor supports six Intel

®

 QuickPath Interconnects at the socket, four full width and 

two half width. The Caching Agent, Home Agent, and Intel

®

 QuickPath Interconnects 

are connected via a 10-port Crossbar Router, each port supporting the Intel

®

 QuickPath 

 shows the processor block diagram. 

Core0

Core3

Core2

Core1

CPE0

CPE3

CPE2

CPE1

Rbox

Bbox0

Zbox0

Zbox1

Bbox1

Pbox  

PZ1

Pbox 

PR1

Pbox 

PR 0

Pbox 

PH4

Pbox 

PH5

Pbox 

PR 3

Pbox 

PR 2

Intel® SMI

Intel® SMI

Intel® 

QPI

Intel® 

QPI

Intel® 

QPI

Intel® 

QPI

Intel® 

QPI

Intel® 

QPI

Pbox  

PZ0

Intel® SMI

Intel® SMI

0xA

0

8

7

3

1

6

9

5

2

4

0xB