Intel 9560 CM8063101049716 Data Sheet

26

The processor has one input reference clock, SYSCLK/SYSCLK_N for the Intel

®

 QPI 

interface. The processor timing specified in this section is defined at the processor pins 
unless otherwise noted. 

Single-ended

GTL I/O

XDPOCPD_N[7:0],TRIGGER_N[1:0]
XDPOCPFRAME_N

GTL Input

XDPOCP_STRB_IN_N, PRBMODE_REQST_N

GTL Output

XDPOCP_STRB_OUT_N, PRBMODE_RDY_N

Core

V

CCCORE

4

Uncore

V

CCUNCORE

4

Cache (Intel

®

 Itanium

®

 

Processor 9300 Series)

V

CCCACHE

4

Analog

V

CCA

I/O

V

CCIO

Stand-by

V

CC33_SM

PIROM

Input

PIR_SCL

I/O

PIR_SDA

Input

PIR_A0

Input

PIR_A1

Input

SM_WP

1. CMOS signals have a reference voltage (Vref) equal to VCCIO/2.

2. GTL signals have a reference voltage (Vref) equal to VCCIO*(2/3).

3. All single-ended buffer types, including inputs, outputs and input/outputs, include an on-die pull up resistor

between 4 kOhms and 8.7 kOhms. Recommended values for external pull-downs on the inputs and input/

output signals must meet the V

il

 specification for that buffer.

fsysclk (ssc-off)

System clock frequency

133.31

133.33

133.34

MHz

Fsyclk (scc-on)

System clock frequency

132.62

132.99

133.37

MHz

ER

sysclk-diff-Rise,

ER

sysclk-diff-Fall

Differential Rising and Falling Edge 

Rates

1.0

4.0

V/ns

3,4

T

sysclk_dutycycle

Duty cycle of Reference clock

40

60

% period

3

C

i-CK

Clock Input Capacitance

0.5

2.0

pf

VH

Differential High Input Voltage

0.15

V

3

VL

Differential Low Input Voltage

-0.15

V

3

V

Cross

Absolute crossing point 

0.25

0.35

0.55

V

1, 5, 6

V

Cross_delta

Peak-peak variation 

140

mv

1, 5, 7

V

RB-Diff

Differential Ringback voltage 

threshold

-100

100

mV

3, 10