Intel 9560 CM8063101049716 Data Sheet

33

The transfer rates available for the processor are shown in 

. Transmitter and 

receiver parameters for Intel

®

 QPI slow mode, Intel

®

 QPI and Intel

®

 SMI are shown in 

 respectively.

The applicability of this section applies to Intel

®

 QPI for the Intel

®

 Itanium

®

 Processor 

9500 Series. This section contains information for slow boot up speed (1/4 frequency of 
the reference clock), 4.8 GT/s, and 6.4 GT/s.

Specifications for link speed independent specifications are called out in 

Electrical specifications for Transmit and Receive for 4.8 GT/s are captured in 

 

and for 6.4 GT/s are captured in 

.

33.33 MHz

66.66 MT/s (see note 1)

2.40 GHz

4.8 GT/s

3.2 GHz

6.4 GT/s

1. This speed is the 1/4 SysClk Frequency.

UIavg

Average UI size at “G” 

GT/s (Where G = 4.8, 

6.4, and so on)

0.999 * 

nominal

1000/G

1.001 * 

nominal

psec

T

slew-rise-fall-pin

Defined as the slope of 

the rising or falling 

waveform as measured 

between ±100mV of the 

differential transmitter 

output, for any data or 

clock

9

20

V/nsec

ΔZ

TX_LOW_CM_DC

Defined as:

(max(Z

TX_LOW_CM_DC

) - 

min(Z

TX_LOW_CM_DC

))

 

/

Z

TX_LOW_CM_DC 

expressed 

in %, over full range of Tx 

single ended voltage

-6

6

% of 

Z

TX_LOW_CM_DC

ΔZ

RX_LOW_CM_DC

Defined as:

(max(Z

TX_LOW_CM_DC

) - 

min(Z

TX_LOW_CM_DC

))

 

/

Z

TX_LOW_CM_DC 

expressed 

in %, over full range of Tx 

single ended voltage

-6

0

6

% of 

Z

TX_LOW_CM_DC

N

MIN-UI-Validation

# of UI over which the 

eye mask voltage and 

timing spec needs to be 

validated

1,000,000

Z

TX_HIGH_CM_DC

Single ended DC 

impedance to GND for 

either D+ or D- of any 

data bit at Tx

4k

Ω

Z

RX_HIGH_CM_DC

Single ended DC 

impedance to GND for 

either D+ or D- of any 

data bit at Rx

4k

Ω

1