Intel 9560 CM8063101049716 Data Sheet

44

 specify static and transient tolerances for the uncore 

outputs. 

7. The FMB remote sense tolerance is ±2.5% for DC to 20 MHz at the package, where ±1.5% is allotted for a DC to 1 MHz range 

and an additional ±1.0% for 1 MHz to 20 MHz. Similarly, ±6.4% is allotted for DC to 20 MHz at the die. It is expected that VCCIO 

regulators meet ±1.5% at the remote sense location based on the general remote sense termination point location as described 

 VR Sense Point (Representation). For future processor compatibility, it is strongly recommended that the platform 

query the PIROM to assure VCCIO is set to the appropriate level prior to powering up the VCCIO supply.

8. All voltage regulation measurements taken at remote sense termination points.

9. For peak-to-peak Ripple and Noise (R&N) measured with full bandwidth (BW) of the scope (Min 1 GHz BW scope is required):    

set scope diff probe and the scope at full BW (capture waveform A, channel 1).

10.For peak-to-peak Ripple and Noise (R&N) measured above 1 MHz: 

 Step 1 = set both: scope diff probe and/or the scope at 1 MHz BW limit (capture waveform B, channel 2)

 Step 2 = calculate A-B (use scope Math function:   subtract channel 1 - channel 2).

I

CC_CORE

I

CC 

for core

35.0

A

1

1. Values per core pair.

I

CC_CORE_TDC

Thermal Design Current for Core

30.0

A

1, 2

2. ICC_CORE_TDC is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely and should be 

used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its 

temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor 

and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see 

the Ararat II Voltage Regulator Module Design Guide for further details. The processor is capable of drawing ICC_CORE_TDC 

indefinitely. 

I

CC_CORE_STEP

Max Load step for core

14.62

A

1, 3

3. During system power on, the pulse inrush (ICC_CORE_STEP) can be as high as 35A peak-to-peak.

d

ICC_CORE/dt

Slew rate for core at Ararat output

34.4

A/us

1

I

CC_UNCORE

I

CC

 for uncore

80.0

A

I

CC_UNCORE_TDC

Thermal Design Current for Uncore

75.0

A

4

4. ICC_UNCORE_TDC is the sustained (DC equivalent) current that the processor uncore is capable of drawing indefinitely and 

should be used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for 

monitoring its temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform 

the processor and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. 

Please see the Ararat II Voltage Regulator Module Design Guide for further details. The processor is capable of drawing 

ICC_UNCORE_TDC indefinitely. This parameter is based on design characterization and is not tested.

I

CC_UNCORE_STEP

Max Load step for uncore

30.4

A

5

5. During system power on, the pulse inrush (ICC_UNCORE_STEP) can be as high as 40A peak-to-peak.

dI

CC_UNCORE/dt

Slew rate for uncore at Ararat output

168.0

A/us

I

CC_IO

I

CC 

for processor I/O

17.2

A

6

6. The ICC_IO current specification applies to the total current from VCCIO pins.

d

ICC_IO/dt

Slew rate for IO at the package pin

54.0

A/us

I

CC_IO_STEP

Max Load step for max slew rate

5.1

A

7

7. The max load step represents the maximum current required during Intel

®

 QPI and Intel

®

 SMI port initialization. The min time 

between steps represents the time between Intel

®

 QPI and Intel

®

 SMI initialization.

T

CC_IO_STEP

Time between steps

4.7

us

7

I

CC_Analog

I

CC

 for processor Analog

4

A

I

CC33_SM

I

CC33

 for main supply

200

mA