Intel Core 2 Extreme QX9300 BX80562QX9300 User Manual

18

Datasheet

operating point. Upon receiving a break event from the package low power state, 

control will be returned to software while an Enhanced Intel SpeedStep Technology 

transition up to the initial operating point occurs. The advantage of this feature is that it 

significantly reduces leakage while in the Stop-Grant and Deeper Sleep states. 

Long-term reliability cannot be assured unless all the Extended Low Power States are 

enabled.

The processor implements two software interfaces for requesting enhanced package 

low power states: MWAIT instruction extensions with sub-state hints and via BIOS by 

configuring IA32_MISC_ENABLES MSR bits to automatically promote package low 

power states to enhanced package low power states. 

remain within specification. As processor technology changes, enabling the 

extended low power states becomes increasingly crucial when building computer 

systems. Maintaining the proper BIOS configuration is key to reliable, long-term 

system operation. Not complying to this guideline may affect the long-term reliability of 

the processor.

that require clocked control. These transitions cannot occur when the processor is in 

the Sleep or Deep Sleep package low power states since processor clocks are not active 

in these states. Extended Deeper Sleep is an exception to this rule when the Hard C4E 

configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended Deeper Sleep 

state configuration will lower core voltage to the Deeper Sleep level while in Deeper 

Sleep and, upon exit, will automatically transition to the lowest operating voltage and 

frequency to reduce snoop service latency. The transition to the lowest operating point 

or back to the original software-requested point may not be instantaneous. 

Furthermore, upon very frequent transitions between active and idle states, the 

transitions may lag behind the idle state entry resulting in the processor either 

executing for a longer time at the lowest operating point or running idle at a high 

operating point. Observations and analyses show this behavior should not significantly 

impact total power savings or performance score while providing power benefits in 

most other cases.

The processor incorporates FSB low power enhancements:

• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On-Die Termination disabling
• Low  V

CCP

 (I/O termination voltage)

The processor incorporates the DPWR# signal that controls the data bus input buffers 

on the processor. The DPWR# signal disables the buffers when not used and activates 

them only when data bus activity occurs, resulting in significant power savings with no 

performance impact. BPRI# control also allows the processor address and control input 

buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows 

a reciprocal power reduction in GMCH address and control input buffers when the 

processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers 

is disabled when the signals are driven low, resulting in additional power savings. The 

low I/O termination voltage is on a dedicated voltage plane independent of the core 

voltage, enabling low I/O switching power at all times.