Intel Core 2 Extreme QX9300 BX80562QX9300 User Manual

Datasheet

21

For clean, on-chip power distribution, the processor will have a large number of V

CC

 

(power) and V

SS

 (ground) inputs. All power pins must be connected to V

CC

 

power 

planes while all V

SS

 pins must be connected to system ground planes. Use of multiple 

power and ground planes is recommended to reduce I*R drop. Refer to the platform 

design guides for more details. The processor V

CC

 pins must be supplied the voltage 

determined by the VID (Voltage ID) pins.

Due to its large number of transistors and high internal clock speeds, the processor is 

capable of generating large average current swings between low and full power states. 

This may cause voltages on power planes to sag below their minimum values if bulk 

decoupling is not adequate. Larger bulk storage, such as electrolytic capacitors, supply 

current during longer lasting changes in current demand by the component, such as 

coming out of an idle condition. Similarly, they act as a storage well for current when 

entering an idle condition from a running condition. Care must be taken in the board 

design to ensure that the voltage provided to the processor remains within the 

specifications listed in 

. Failure to do so may result in timing violations or 

reduced lifetime of the component.

V

CC 

regulator solutions need to provide bulk capacitance with a low Effective Series 

Resistance (ESR) and keep a low interconnect resistance from the regulator to the 

socket. Bulk decoupling for the large current swings when the part is powering on, or 

entering/exiting low-power states, should be provided by the voltage regulator solution 

depending on the specific system design.

The processors integrate signal termination on the die as well as incorporate high 

frequency decoupling capacitance on the processor package. Decoupling must also be 

provided by the system motherboard for proper AGTL+ bus operation.

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the 

processor. As in previous-generation processors, the processor core frequency is a 

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its 

default ratio at manufacturing.The processor uses a differential clocking 

implementation.