Intel i5-4300Y CL8064701558601 Data Sheet

eDP_TXP[3:0]
eDP_TXN[3:0]

embedded DisplayPort Transmit Differential Pair

O

eDP

eDP_AUXP
eDP_AUXN

embedded DisplayPort Auxiliary Differential Pair

O

eDP

eDP_RCOMP

embedded DisplayPort Current Compensation

I/O

A

eDP_DISP_UTIL

Low voltage multipurpose DISP_UTIL pin on the

processor for backlight modulation control of

embedded panels and S3D device control for active

shutter glasses. This pin will co-exist with

functionality similar to existing BKLTCTL pin on the

PCH.

O

Asynchronous CMOS

DDIB_TXP[3:0]
DDIB_TXN[3:0]

Digital Display Interface Transmit Differential Pair

O

DP*/HDMI*

DDIC_TXP[3:0]
DDIC_TXN[3:0]

Digital Display Interface Transmit Differential Pair

O

DP*/HDMI*

BPM#[7:0]

Outputs from the processor that indicate the status of

breakpoints and programmable counters used for

monitoring processor performance.

I/O

GTL

PRDY#

Processor Ready: This signal is a processor output

used by debug tools to determine processor debug

readiness.

O

GTL

PREQ#

Processor Request: This signal is used by debug tools

to request debug operation of the processor.

I

GTL

PROC_TCK

Test Clock: This signal provides the clock input for the

processor Test Bus (also known as the Test Access

Port). This signal must be driven low or allowed to float

during power on Reset.

I

GTL

PROC_TDI

Processor Test Data In: This signal transfers serial

test data into the processor. This signal provides the

serial input needed for JTAG specification support.

I

GTL

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 329001-007

77