Intel i5-4300Y CL8064701558601 Data Sheet

Single ended

GTL

CATERR#

Single ended

Asynchronous

CMOS Input

RESET#, PROCPWRGD, PWR_DEBUG# , VCCST_PWRGD

Single ended

Asynchronous Bi-

directional

PECI

Single ended

GTL Bi-directional

CFG[19:0]

Single ended

VR Enable CMOS

Output

VR_EN

Single ended

CMOS Input

VR_READY

Single ended

CMOS Input

VIDALERT#

Single ended

Open Drain Output

VIDSCLK

Single ended

CMOS I/O

VIDSOUT

Differential

Analog Output

VCC_SENSE, VSS_SENSE

Single ended

Power

VCC, VDDQ, VCCST

Ground

VSS, VSS_NCTF 

3

No Connect

RSVD, RSVD_NCTF

Test Point

RSVD_TP

Other

DAISY_CHAIN_NCTF_[ball #]

Differential

DDI Output

DDIB_TXP[3:0], DDIB_TXN[3:0], DDIC_TXP[3:0],

DDIC_TXN[3:0]]

Notes: 1. See 

 on page 72 for signal description details.

2. SA and SB refer to DDR3L/DDR3L-RS Channel A and DDR3L/DDR3L-RS Channel B.

Due to the voltage levels supported by other components in the Test Access Port

(TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any

other components within the system. A translation buffer should be used to connect to

the rest of the chain unless one of the other components is capable of accepting an

input of the appropriate voltage. Two copies of each signal may be required with each

driving a different voltage level.

The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE

1149.6-2003 standards. A few of the I/O pins may support only one of those

standards.

The processor DC specifications in this section are defined at the processor pins,

 on page 72 for the processor pin

listings and signal definitions.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 329001-007

89