Intel 2955U CL8064701523900 Data Sheet

Product codes
CL8064701523900
Page of 123
System Memory Timing Support
The IMC supports the following DDR3L/DDR3L-RS Speed Bin, CAS Write Latency
(CWL), and command signal mode timings on the main memory interface:
tCL = CAS Latency
tRCD = Activate Command to READ or WRITE Command delay
tRP = PRECHARGE Command Period
CWL = CAS Write Latency
Command Signal modes = 1N indicates a new command may be issued every
clock and 2N indicates a new command may be issued every 2 clocks. Command
launch mode programming depends on the transfer rate and memory
configuration.
Table 7.
DRAM System Memory Timing Support
Segment
DRAM
Device
Transfer
Rate
(MT/s)
tCL
(tCK)
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK)
DPC
(SO-
DIMM
Only)
CMD
Mode
U-Processor /
Y-Processor
(Dual Core)
DDR3L/
DDR3L-RS
1333
8/9
8/9
8/9
7
1
1N/2N
LPDDR3
1333
10
12
12
7
1
0.5N
DDR3L/
DDR3L-RS
1600
10/11
10/11
10/11
8
1
1N/2N
LPDDR3
1600
12
15
15
8
1
0.5N
System Memory Organization Modes
The Integrated Memory Controller (IMC) supports two memory organization modes –
single-channel and dual-channel. Depending upon how the DIMM Modules are
populated in each memory channel, a number of different configurations can exist.
Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
Dual-Channel Mode – Intel
®
 Flex Memory Technology Mode
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into
symmetric and asymmetric zones. The symmetric zone starts at the lowest address in
each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note: 
Channels A and B can be mapped for physical channel 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
2.1.2  
2.1.3  
Interfaces—Processors
Mobile 4th Generation Intel
®
 Core
 Processor Family, Mobile Intel
®
 Pentium
®
 Processor Family, and Mobile Intel
®
 Celeron
®
Processor Family
July 2014
Datasheet – Volume 1 of 2
Order No.: 329001-007
19