Intel 2955U CL8064701523900 Data Sheet

The Adaptive Thermal Monitor does not require any additional hardware, software

drivers, or interrupt handling routines. It is not intended as a mechanism to maintain

processor TDP. The system design should provide a thermal solution that can maintain

TDP within its intended usage range.

Adaptive Thermal Monitor protection is always enabled.

TCC Activation Offset can be used to activate the Adaptive Thermal Monitor at

temperatures lower than Tj

MAX

. It is the preferred thermal protection mechanism for

Intel Turbo Boost Technology 2.0 operation since ACPI passive throttling states will

pull the processor out of turbo mode operation when triggered. An offset (in degrees

Celsius) can be written to the TEMPERATURE_TARGET (0x1A2) MSR, bits [29:24]. This

value will be subtracted from the value found in bits [23:16]. The default offset is

0 °C, TCC activation will occur at Tj

MAX

. The offset should be set lower than any other

protection such as ACPI _PSV trip points.

Upon Adaptive Thermal Monitor activation, the processor core attempts to dynamically

reduce processor core power by lowering the frequency and voltage operating point.

The operating points are automatically calculated by the processor core itself and do

not require the BIOS to program them as with previous generations of Intel

processors. The processor core will scale the operating points such that:
•

The voltage will be optimized according to the temperature, the core bus ratio,

and number of cores in deep C-states.

•

The core power and temperature are reduced while minimizing performance

degradation.

Once the temperature has dropped below the maximum operating temperature, the

operating frequency and voltage will transition back to the normal system operating

point.

Once a target frequency/bus ratio is resolved, the processor core will transition to the

new target automatically.
•

On an upward operating point transition, the voltage transition precedes the

frequency transition.

•

On a downward transition, the frequency transition precedes the voltage

transition.

•

The processor continues to execute instructions. However, the processor will halt

instruction execution for frequency transitions.

If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition

(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there

are two possible outcomes:
•

If the P-state target frequency is higher than the processor core optimized target

frequency, the P-state transition will be deferred until the thermal event has been

completed.

•

If the P-state target frequency is lower than the processor core optimized target

frequency, the processor will transition to the P-state operating point.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

66

Order No.: 329001-007