Intel 2955U CL8064701523900 Data Sheet

SB_DQ[63:0]

Data Bus: Channel A data signal interface to the SDRAM data

bus.

I/O

SB_DQSP[7:0]
SB_DQSN[7:0]

Data Strobes: SB_DQS[7:0] and its complement signal group

make up a differential strobe pair. The data is captured at the

crossing point of SB_DQS[7:0] and its SB_DQS#[7:0] during

read and write transactions.

I/O

SB_CAA[9:0]

Command Address: These signals are used to provide the

multiplexed command and address to the SDRAM.

O

SB_CAB[9:0]

Command Address: These signals are used to provide the

multiplexed command and address to the SDRAM.

O

SB_CKP[1:0]
SB_CKN[1:0]

SDRAM Differential Clock: Channel A SDRAM Differential

clock signal pair. The crossing of the positive edge of SB_CKP

and the negative edge of its complement SB_CKN are used to

sample the command and control signals on the SDRAM.

O

SB_CS#[1:0]

Chip Select: (1 per rank). These signals are used to select

particular SDRAM components during the active state. There is

one Chip Select for each SDRAM rank.

O

SB_CKE[3:0]

Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up
• Power down SDRAM ranks.
• Place all SDRAM into and out of self-refresh during STR.
• When 1R LPDDR3 CKE[0] and CKE[2] are used for Rank0
• When 2R LPDDR3 CKE[0] and CKE[2] are used for Rank 0

and CKE[1] and CKE[3] are used for Rank 1

O

SB_ODT

On Die Termination: Active Termination Control.

O

SM_RCOMP[2:0]

I

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

The output pins are connected to the MD/DIMMs, and holds

VDDQ/2 as reference voltage.

O

SM_PG_CNTL1

System Memory Power Gate Control: This signal

disables the platform memory VTT regulator in C8 and

deeper and S3 states.

CMOS OUTPUT

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 329001-007

75