Intel i3-4020Y CL8064701512402 Data Sheet

C1/C1E is a low power state entered when all threads within a core execute a HLT or

MWAIT(C1/C1E) instruction.

A System Management Interrupt (SMI) handler returns execution to either Normal

state or the C1/C1E state. See the Intel

Developer’s Manual for more information.

While a core is in C1/C1E state, it processes bus snoops and snoops from other

threads. For more information on C1E state, see 

 on page 48.

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to

the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its

L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while

maintaining its architectural state. All core clocks are stopped at this point. Because

the core’s caches are flushed, the processor does not wake any core that is in the C3

state when either a snoop is detected or when another core accesses cacheable

memory.

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or

an MWAIT(C6) instruction. Before entering core C6 state, the core will save its

architectural state to a dedicated SRAM. Once complete, a core will have its voltage

reduced to zero volts. During exit, the core is powered on and its architectural state is

restored.

Individual threads of a core can enter the C7, C8, C9, or C10 state by initiating a

P_LVL4, P_LVL5, P_LVL6, P_LVL7 I/O read (respectively) to the P_BLK or by an

MWAIT(C7/C8/C9/C10) instruction. The core C7–C10 state exhibits the same behavior

as the core C6 state.

In general, deeper C-states, such as C6 or C7 state, have long latencies and have

higher energy entry/exit costs. The resulting performance and energy penalties

become significant when the entry/exit frequency of a deeper C-state is high.

Therefore, incorrect or inefficient usage of deeper C-states have a negative impact on

battery life and idle power. To increase residency and improve battery life and idle

power in deeper C-states, the processor supports C-state auto-demotion.

There are two C-state auto-demotion options:
•

C7/C6 to C3 state

•

C7/C6/C3 To C1 state

The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 state is based on

each core’s immediate residency history and interrupt rate . If the interrupt rate

experienced on a core is high and the residence in a deep C-state between such

interrupts is low, the core can be demoted to a C3 or C1 state. A higher interrupt

pattern is required to demote a core to C1 state as compared to C3 state.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 329001-007

47